Formation of low K material utilizing process having readily cleaned by-products

Abstract

Nano-porous low dielectric constant films are deposited utilizing materials having reactive by-products readily removed from a processing chamber by plasma cleaning. In accordance with one embodiment, an oxidizable silicon containing compound is reacted with an oxidizable non-silicon component having thermally labile groups, in a reactive oxygen ambient and in the presence of a plasma. The deposited silicon oxide film is annealed to form dispersed microscopic voids or pores that remain in the nano-porous silicon. Oxidizable non-silicon components with thermally labile groups that leave by-products readily removed from the chamber, include but are not limited to, limonene, carene, cymene, fenchone, vinyl acetate, methyl methacrylate, ethyl vinyl ether, tetrahydrofuran, furan, 2,5 Norbornadiene, cyclopentene, cyclopentene oxide, methyl cyclopentene, 2-cyclopentene-1-one, and 1-butene.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The instant nonprovisional patent application claims priority from provisional patent application No. 60 / 645,082, filed Jan. 18, 2005 and incorporated herein by reference for all purposes.BACKGROUND OF THE INVENTION[0002]One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, en...

AI Technical Summary

Problems solved by technology

The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate.

However, the barrier / liner layers typically have dielectric constants that are greater than about 2.5, and the high dielectric constants result in a combined insulator that may not significantly reduce the dielectric constant.

Additionally, the smaller device geometries result in an increase in parasitic capacitance between devices.

Parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit can result in crosstalk between the metal lines or interconnects and / or resistance-capacitance (RC) delay, thereby reducing the response time of the device and degrading the overall performance of the device.

Increasing the thickness of the dielectric materials, however, does not address parasitic capacitance within the same metallized layer or plane.

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