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Split grid flash internal memory unit character line structure and its manufacturing method

A technology of memory cells and separated gates, which is applied in semiconductor/solid-state device manufacturing, electrical components, and electric solid-state devices, etc. Memory cell electrical quality and process reliability issues

Inactive Publication Date: 2008-03-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] When the above-mentioned prior art utilizes the etching method to manufacture word lines of split gate flash memory cells, not only is it difficult to effectively control the key dimensions of the memory cells, but also the spacers of the word lines cannot form a better square structure. A fence-like structure is formed on the wall, which seriously affects the electrical quality and process reliability of the memory unit

Method used

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  • Split grid flash internal memory unit character line structure and its manufacturing method
  • Split grid flash internal memory unit character line structure and its manufacturing method
  • Split grid flash internal memory unit character line structure and its manufacturing method

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Embodiment Construction

[0020] In order to make the description of the present invention more detailed and complete, please refer to FIG. 8 to FIG. 15 . FIG. 8 to FIG. 15 are process cross-sectional views of a word line of a split-gate flash memory cell according to a preferred embodiment of the present invention. Firstly, a gate dielectric layer 202 is formed on the semiconductor substrate 200 by thermal oxidation, wherein the material of the gate dielectric layer 202 can be, for example, silicon oxide. The conductive layer 204 is then formed by chemical vapor deposition (CVD), wherein the material of the conductive layer 204 is preferably polysilicon. The above-mentioned gate dielectric layer 202 and conductive layer 204 are material layers for making the floating gate. Next, a nitride layer 206 is formed to cover the conductive layer 204 by means of, for example, chemical vapor deposition. After the nitride layer 206 is formed, a defined step is performed by using, for example, lithography and et...

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Abstract

In the method, material layer of word line is formed on gate structure, and cover layer is formed on the material layer of word line. Then, partial cover layer and partial material layer of word line are removed by using technique of chemical mechanical pulverization (CMP). After oxide layer is formed on surface of exposed material layer of word line, removing remaining cover layer and its material layer of word line forms box-shape word line of split gate flash memory cell.

Description

technical field [0001] The present invention relates to a word line (Word Line) of a split gate flash memory unit (Split Gate Flash Memory Cell) and a manufacturing method thereof, in particular to a method of manufacturing a split gate flash by using chemical mechanical polishing (CMP) technology The method of the square (Box-shape) word line of the memory unit. Background technique [0002] Among the flash memory devices, compared with the stacked gate flash memory device, the split gate flash memory device is not only smaller in size, but also saves more power. Therefore, split-gate flash memory has become a very popular storage device at present. In the split gate flash memory, polysilicon spacers are usually used as word lines to reduce the size of the split gate flash memory. [0003] Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are process cross-sectional views of word lines of conventional split-gate flash memory cells. Firstly, an oxide layer 102 , a polys...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/8239H01L27/105H10B99/00
Inventor 喻中一罗际兴蔡嘉雄
Owner TAIWAN SEMICON MFG CO LTD