Split grid flash internal memory unit character line structure and its manufacturing method
A technology of memory cells and separated gates, which is applied in semiconductor/solid-state device manufacturing, electrical components, and electric solid-state devices, etc. Memory cell electrical quality and process reliability issues
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[0020] In order to make the description of the present invention more detailed and complete, please refer to FIG. 8 to FIG. 15 . FIG. 8 to FIG. 15 are process cross-sectional views of a word line of a split-gate flash memory cell according to a preferred embodiment of the present invention. Firstly, a gate dielectric layer 202 is formed on the semiconductor substrate 200 by thermal oxidation, wherein the material of the gate dielectric layer 202 can be, for example, silicon oxide. The conductive layer 204 is then formed by chemical vapor deposition (CVD), wherein the material of the conductive layer 204 is preferably polysilicon. The above-mentioned gate dielectric layer 202 and conductive layer 204 are material layers for making the floating gate. Next, a nitride layer 206 is formed to cover the conductive layer 204 by means of, for example, chemical vapor deposition. After the nitride layer 206 is formed, a defined step is performed by using, for example, lithography and et...
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