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Semiconductor chip buried base plate 3D construction and its manufacturing method

A manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., can solve problems such as unstable quality of the overall assembly structure, difficulty in filling insulating materials, and generation of popcorn. , to achieve good quality and product reliability, improve the rate of good, and increase the effect of output

Active Publication Date: 2009-02-18
PHOENIX PRECISION TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the gap is small, and it is difficult to fill it with insulating materials such as resin. During the filling process, air bubbles are easily generated in the gap, which will cause popcorn phenomenon in the subsequent heating process, resulting in unstable quality of the overall structure.

Method used

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  • Semiconductor chip buried base plate 3D construction and its manufacturing method
  • Semiconductor chip buried base plate 3D construction and its manufacturing method
  • Semiconductor chip buried base plate 3D construction and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0026] see Figure 4A , first provide the carrier 400 having the through hole 400a. The carrier 400 can be an insulating core board, a metal plate or a circuit board with circuits, and the thickness of the carrier 400 can be determined as required.

[0027] see Figure 4B , and then bonding the carrier 400 on the first insulating layer 401 . The first insulating layer 401 can be prepreg or film material, such as epoxy resin, polyimide, LCP, bismaleimide / Triple nitrogen trap (BT, Bismaleimide triazine), ABF (Ajinomoto Build-up Film), polyphenylene ether (PPE), polytetrafluoroethylene (PTFE), benzocyclobutene (BCB, benzocylobutene), etc.

[0028] see Figure 4CA non-circuit surface 430 of a semiconductor chip 43 is placed on the first insulating layer 401 by means of a thermally conductive adhesive layer 42 and accommodated in the opening 400 a of the carrier 400 . The chip 43 has a plurality of electrode pads 431 a on the circuit surface 431 .

[0029] see Figure 4D , ...

Embodiment 2

[0034] see Figures 5A to 5H , which are schematic cross-sectional views of Embodiment 2 of the manufacturing method of the semiconductor package structure of the present invention. Embodiment 2 of the semiconductor package structure and its manufacturing method of the present invention is similar to Embodiment 1, the main difference is that a heat dissipation blind hole connecting the non-circuit surface of the semiconductor chip is formed in the first insulating layer, and the heat dissipation blind hole is filled with heat dissipation material And connected to the heat conduction circuit layer in the circuit structure, and then connected to the outside, or can further provide direct external connection with other heat dissipation devices to improve the heat dissipation effect of the semiconductor package structure.

[0035] see Figure 5A , first provide a carrier 500 having a through hole 500a. The carrier 500 can be an insulating core board, a metal plate or a circuit b...

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Abstract

This invention relates to semiconductor chip imbed baseboard three dimensional seal structure and its process method, which comprises the following steps: connecting load parts with at least one hole to first insulation layer and at least one conductor chip onto first insulation contained in the load holes; then forming second insulation layer onto load part and chips for adhesion and filling insulation resin into gap between load board and chip to form electricity connection to chip circuit layer; forming chip dissipation blind hole on first insulation layer to aid semiconductor chip to dissipate heat outside.

Description

technical field [0001] The present invention relates to a three-dimensional structure of a semiconductor chip embedded in a substrate and a manufacturing method thereof, in particular to a semiconductor structure integrating a chip and a carrier and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronic industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, circuit boards that provide multiple active and passive components and circuit connections have gradually evolved from single-layer boards to multi-layer boards. Multi-layer board (Multi-layer bord), in a limited space, uses the interlayer connection technology (Interlayer connection) to expand the available circuit area on the circuit board to meet the needs of integrated circuits...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L23/31H01L23/488H01L23/36
CPCH01L2924/0002H01L2224/2518H01L24/19H01L2224/16225H01L2224/04105H01L2224/12105H01L2224/19H01L2224/73267H01L2924/14H01L2924/00H01L2924/00012
Inventor 许诗滨
Owner PHOENIX PRECISION TECH CORP
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