Solid-state imaging device and camera
A technology of solid-state imaging device and imaging area, which is applied to electric solid-state devices, semiconductor devices, electrical components, etc., can solve problems such as large noise and leakage current leakage, and achieve the effect of reducing noise and high practical value.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 approach
[0037] 4 is a cross-sectional view showing an example of the structure of the n-channel MOS transistor and the trench element isolation portion constituting the imaging region of the MOS solid-state imaging device 110 according to the first embodiment of the present invention. The MOS transistor is separated from the adjacent MOS transistor by the element isolation portion 2, and the photodiode 3 forms an n-type diffusion region in the silicon wafer (or P-type well) 1. The photodiode 3 also serves as the source of the MOS transistor in the imaging area. Like other MOS transistors, an element isolation portion 2 is formed in the area adjacent to the photodiode 3.
[0038] Furthermore, it is desirable to form a p-type diffusion region as the dark current suppression layer 6 in the vicinity of the surface of the n-type diffusion region as the photodiode 3. In this case, the dark current suppression layer 6 extends to the periphery of the element isolation portion 2 as shown in FIG. 4...
no. 2 approach
[0056] In the MOS-type solid-state imaging device according to this embodiment, the imaging area and the peripheral circuit are composed of a plurality of MOS transistors electrically isolated by an element isolation portion. FIG. 10 shows the structure of the element isolation portion between MOS transistors in the imaging area or in the peripheral circuit, and is a cross-sectional view showing that the transistor 40 and the transistor 41 are electrically isolated by the element isolation portion 42. The element isolation portion 42 erodes the silicon wafer 1 to a depth of 1 nm or more and 200 nm or less, and can generate leakage current between the active region 43 of the transistor 40 and the active region 44 of the transistor 41. As shown in FIG. 10, an impurity diffusion layer 45 for suppressing leakage is provided directly under the element isolation portion 42. This can increase the withstand voltage related to the leakage current between the transistors electrically isolat...
no. 3 approach
[0058] 11 shows an example of the structure of the element isolation portion between the MOS transistors in the imaging area or in the peripheral circuit in the MOS type solid-state imaging device according to the third embodiment, and shows that the transistor 46 and the transistor 47 pass through the element isolation portion 48 A cross-sectional view of the state of electrical isolation. As described above, the crystal structure of the interface between the element isolation portion 48 and the silicon wafer 1 is in a disordered state, and leakage current is generated. Therefore, on the silicon wafer 1 side of the interface between the element isolation portion 48 and the silicon wafer 1 formed, the impurity diffusion layer 51 is formed along the sidewall of the element isolation portion and the interface of the silicon wafer 1, thereby suppressing the element isolation portion 48 The interface level with silicon wafer 1 leaks.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More