Power gate control circuit for restraining power/grounding line network voltage jitter

Abstract

The power gate circuit for inhibiting power / ground network voltage jittering applies a controlled diode to switch circuit from sleep mode to normal work mode with smooth current. This invention reduces instant peak current on switching moment, and decreases voltage fluctuation.

Description

technical field [0001] The application field of "Power Gating Circuit for Suppressing Power / Ground Network Voltage Jitter" is the design of low-power large-scale integrated circuits. The proposed circuit is suitable for fast mode (sleeping, working, waiting) switching of integrated circuits. While increasing the switching speed, it can greatly reduce the interference of the instantaneous inrush current on adjacent circuits during switching, and effectively suppress Leakage current in active mode. Background technique [0002] With the gradual reduction of the feature size of the CMOS process, the leakage problem in the integrated circuit becomes more and more serious. Compared with the old technology of the previous generation, the leakage power consumption of each new generation technology increases by about 30 times. For a CMOS transistor, the leakage current in the subthreshold region between the drain and source of the transistor dominates, and its expression is as fol...

AI Technical Summary

Problems solved by technology

This technology can greatly reduce leakage power consumption, but there are also some shortcomings. In the article "Understanding and minimizing ground bounce during mode transition of power gating structures" by S.Kim et al., a shortcoming of power gating technology is mentioned: using The circuit of power gating technology, when switching from sleep mode to normal operation mode, will cause the problem of voltage jitter of power supply and ground network, because in the sleep state, the capacitor in the circuit stores a large amount of charge, and when switching to normal operation When in power mode, these charges are poured from the sleep transistor to the ground network at once, forming a large inrush current. Due to the parasitic distributed resistance in the power supply and the bottom line network, the inrush current will further cause voltage jitter

However, the disadvantage of such a circuit is that the complexity of the control circuit is relatively high

The control steps are more complicated

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