1results about How to "Reduce inrush current" patented technology

The utility model relates to the field of switching circuits, in particular to a PMOS (P-channel Metal Oxide Semiconductor) switching circuit, which is characterized in that a source electrode of a PMOS tube Q1 is connected with an input voltage end Vi n, and a drain electrode is connected with a load output end Vout; a base electrode of the triode Q2 receives the switching signal through a control signal end PWR, and an emitting electrode of the triode Q2 is grounded; the first divider resistor R1 is connected between the grid electrode of the PMOS tube Q1 and an input voltage end Vi n; the second divider resistor R2 is connected between the grid electrode of the PMOS tube Q1 and the collector electrode of the triode Q2; the first capacitor C1 is connected between the grid electrode and the source electrode of the PMOS tube Q1; the resistance value ratio of the first divider resistor R1 to the second divider resistor R2 is 1: 3 to 1: 5, the capacitance value of the first capacitor C1 is 10 nF to 100 nF, and the load capacitance C2 does not exceed 470 [mu] F. The voltage division ratio of R1 / R2 is matched with the capacitor C1, so that the conduction time of the PMOS is prolonged, the instantaneous charging current peak value of the load capacitor C2 is remarkably reduced, voltage drop is avoided, and the stability of the system is guaranteed.