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Substrates bar, substrate structure and manufacturing method thereof

A manufacturing method and substrate strip technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as no way to know, increase product yield, process monitoring and troubleshooting difficulties, etc., to improve product quality Yield, time and cost reduction effects

Active Publication Date: 2009-10-21
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, once the packaging substrate strip 100 is bonded to the chip and the packaging process is completed, since the separation process will be performed to separate the substrate unit 110 from the substrate frame 120, if the quality of the separated packaging structures is limited When there is a problem, it is impossible to know the manufacturing batch number of the packaging substrate strip 100 used in these independent packaging structures, which will easily lead to increased difficulty in process monitoring and troubleshooting and a decrease in product yield.
[0004] Therefore, there is a great need for an improved packaging substrate strip to solve the problem that it is difficult to monitor process variation and troubleshoot in the existing process, so as to achieve the purpose of improving product quality and process yield

Method used

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  • Substrates bar, substrate structure and manufacturing method thereof
  • Substrates bar, substrate structure and manufacturing method thereof
  • Substrates bar, substrate structure and manufacturing method thereof

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Embodiment Construction

[0016] see Figure 2A to Figure 2J As shown, it is mainly a cross-sectional schematic diagram drawn according to the manufacturing process of a preferred embodiment of the substrate structure of the present invention.

[0017] First, if Figure 2A As shown, a core substrate 200 is provided, which has a top surface 200a and a bottom surface 200b opposite to the top surface 200a, wherein the top surface 200a and the bottom surface 200b each have a circuit pattern 210, 212 (ie, the first circuit pattern and the second circuit pattern) two-line pattern). The core substrate 200 has at least one via hole (not shown), and a conductive layer 202 is disposed in the via hole for electrically connecting the circuit patterns 210 and 212 , and an insulating material 204 is provided to plug the via hole.

[0018] Next, if Figure 2B As shown, ILD layers 220 , 222 (ie, a first ILD layer and a second ILD layer) are respectively formed on the top surface 200 a and the bottom surface 200 b t...

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Abstract

The invention discloses a substrate structure and a manufacturing method thereof. The substrate structure at least includes a core substrate, a build-up part and a solder mask. The core substrate includes a top surface and a bottom surface opposite to the top surface, and a circuit pattern is formed on the top surface. The build-up part is disposed on the top surface, wherein the build-up part at least includes a surface dielectric layer and a surface circuit layer above the surface dielectric layer, and the surface circuit layer is electrically connected to the circuit pattern. The solder resist layer is disposed on the build-up part, wherein the solder resist layer has at least one hole, and the hole is used to identify the substrate structure.

Description

【Technical field】 [0001] The invention relates to a substrate strip and a substrate structure and a manufacturing method thereof, in particular to a substrate strip and a substrate structure with identification marks and a manufacturing method thereof. 【Background technique】 [0002] Today, with the rapid development of social informatization, in order to meet the requirements of high-speed processing, multi-functionality, integration, small size and light weight of electronic devices, semiconductor process technology is also constantly developing towards miniaturization and high density. In order to reduce the packaging volume and improve the functionality of package components, advanced packaging technologies such as flip chip (Flip chip, FC) packaging, ball grid array (Ball Grid Array, BGA) packaging and chip scale packaging (Chip Scale Package, CSP) are now available. It has been widely used in the industry, and the substrate type carrier is a frequently used component i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L23/544H01L21/48H01L21/00
Inventor 詹淑銮吕志淦黄吉志张硕训
Owner ADVANCED SEMICON ENG INC
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