Stack grid-source one-side electronic injection flash memory and manufacturing method thereof
A technology of electron injection and manufacturing method, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, circuits, etc., and can solve problems such as slow reading and writing speed
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Embodiment 1
[0026] Taking an n-channel flash memory cell as an example, the structure of the stacked gate-source side electron injection flash memory according to the present invention is described. As shown in FIG. 3, the stacked gate-source side electron injection flash memory according to the present invention includes: a source and a drain formed from a p-well formed in a semiconductor substrate, and between said source and the drain Floating gate and control gate formed sequentially above the p-well. It can be seen from FIG. 3 that the floating gate includes two oxide regions with different thicknesses, namely region A and region B.
[0027] Area A is the tunnel area, and nitrogen (N) ions are implanted in the tunnel area. During the thermal oxidation process, the growth rate of the oxide layer is slow due to the implanted nitrogen ions; area B is the gate area, and nitrogen is not implanted in the gate area B. (N) ions, the growth rate of the oxide layer is fast during the thermal ...
Embodiment 2
[0032] Taking the n-channel flash memory cell as an example, the method of manufacturing the stacked gate-source side electron injection flash memory according to the present invention will be described. Of course, the same process can also be used to manufacture p-channel flash memory cells, but the process parameters need to be adjusted appropriately.
[0033] The method for manufacturing the stack gate-source side electron injection flash memory according to the present invention comprises the following process steps:
[0034] (a) Use a p-type semiconductor wafer as a substrate, first determine the active area (AA), and form an isolation area [STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon)];
[0035] (b) As shown in Figure 7, a deep n-well is formed, and a p-well is formed on the deep n-well, and an electric field is applied for ion implantation, and a threshold voltage is used to adjust the implanted ion concentration to prevent penetration ion implan...
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