High-performance time-digital converter circuit structure
A converter circuit, time-to-digital technology, applied in time-to-digital converters, analog-to-digital converters, instruments, etc., can solve the problems of unrealistic charging current, large charging current, slow capacitance, etc., to ensure correctness and processing speed. Fast and accurate timing effect
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[0038] As shown in Figure 1, a high-performance time-to-digital converter circuit architecture includes a delay chain loop (10) that generates low-bit data, a counter (20) that generates high-bit data, and a compensation control source (30).
[0039] As shown in Figure 2, the delay chain loop (10) consists of a delay unit loop (101), a set of comparators (102), a set of latches (103), an encoder (104) and an initialization unit ( 105) Composition.
[0040]The delay unit loop (10) is composed of n (n is a positive integer) buffers, each buffer Buffer has two positive and negative differential input terminals and two positive and negative differential output terminals, each level of buffer Buffer and The non-inverting end of the next-level buffer Buffer is connected, the positive output end of the last-level buffer Buffer is connected to the negative input end of the first-level buffer Buffer, and the negative output end is connected to the positive input end of the first-level buff...
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