Semiconductor device and its manufacturing method

Abstract

The thickness and occupied area are reduced compared with conventional methods when semiconductor chips are three-dimensionally arranged, low-cost mounting is realized without using any other components, and the manufacturing process of the semiconductor device is simplified. A flip-chip mounting structure in which a first semiconductor chip (101) thinned by back-grinding and a substrate (105) are directly connected to a wiring pattern (106) through bump electrodes (102) is fabricated. For example, an electrode (104) higher than the sum of the thickness of the first semiconductor chip (101) and the electrode (102) is formed on a second semiconductor chip (103) and connected directly to the wiring pattern (106) on the substrate (105), thus providing a most-compact, three-dimensional semiconductor mounted device.

Description

technical field [0001] The present invention relates to a semiconductor device formed by three-dimensionally mounting a plurality of semiconductor chips on a common substrate by flip-chip mounting and a method of manufacturing the same. Background technique [0002] In order to achieve high density and miniaturization of semiconductor devices, semiconductor chips are often mounted on substrates by flip-chip mounting. Flip-chip mounting is a mounting method in which a bare semiconductor chip without a package structure is mounted in a flip-chip state on a wiring pattern of a substrate. [0003] Conventionally, there has been proposed a mounting structure in which another semiconductor chip is laminated on one flip-chip mounted semiconductor chip (or another semiconductor chip is three-dimensionally arranged on one semiconductor chip), so that the mounting area can be minimized. shrinkage (Patent Documents 1 to 3). [0004] In Patent Document 1, another semiconductor chip is...

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Problems solved by technology

[0009] In the mounting technique described in Patent Document 1, the thickness of the semiconductor device becomes thicker due to the wiring height of the wire bonding and the thickness of the resin used to seal the lead portion

In addition, since the bonding wires also extend in the lateral direction, it is not necessarily possible to achieve the effect of reducing the area compared to the case where the semiconductor chips are arranged in a planar manner.

[0010] In addition, in the mounting technology described in Patent Document 2 or Patent Document 3, a dedicated relay substrate (relay component) occupies a relatively large area, so that the occupied area of ​​the semiconductor device is correspondingly enlarged in the lateral direction. In this case, compared with the case where the semiconductor chips are arranged planarly, the effect of reducing the area may not be obtained.

In addition, since the thickness of the dedicated interposer (interconnect part) increases the thickness of the semiconductor device accordingly, it cannot be asserted that a sufficient effect of volume reduction can be obtained, and there may be cases where the use of the interposer (interconnect part) Relay parts) resulting in higher costs

[0011] As described above, in the conventional mounting technology, when stacking (or three-dimensionally mounting) a plurality of semiconductor chips, compared with the case of arranging each chip in a planar manner, the effect of area and volume reduction or cost there are some deficiencies

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