Adulation method for MOS transistor body area

A technology of MOS transistor and body region, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as reduced carrier mobility, increased parasitic capacitance and leakage current, and leakage parasitic resistance.

Inactive Publication Date: 2008-03-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, the continuous increase of doping concentration will lead to problems such as the decrease of carrier mobility, the deterioration of subthreshold characteristics, and the difficulty in reducing the threshold voltage.
The Halo (pocket) doping method alleviates the above problems to a certain extent, but there are still problems such as source-drain parasitic resistance, parasitic capacitance and leakage current increase.

Method used

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  • Adulation method for MOS transistor body area
  • Adulation method for MOS transistor body area
  • Adulation method for MOS transistor body area

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Embodiment Construction

[0040] The preferred embodiment of the present invention is described in more detail below with reference to the accompanying drawings of the present invention.

[0041] (1) The substrate is a bulk silicon wafer

[0042] A specific example of the fabrication method for preparing an integrated silicon MOS transistor is shown in Figures 1 to 6, including the following steps:

[0043] 1) As shown in Figure 1, the crystal orientation of the single crystal silicon substrate used is (100), and for n-type MOS transistors, the body region 1 is initially lightly doped with p-type. For p-type MOS transistors, body region 1 is initially lightly doped with n-type. The active region isolation layer 2 is fabricated by using conventional CMOS shallow trench isolation technology. Next, a gate dielectric layer 3 is grown. The gate dielectric layer 3 is silicon dioxide with a thickness of 0.5-3 nm. The gate dielectric can also be formed by one of the following methods: conventional thermal ...

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Abstract

This invention provides a doping method for MOS transistor region, which forms a slot at either side of a grid to inject and dope to the transistor region via the slot so as to realize that heavy doped regions at both sides of a channel region are shown as strips, which can shield the influence of the drain field to the channel and source effectively so the device has a good short channel property, since the strip heavy doped regions are at both sides of the channel, the concentration of impurity in the channel region is very low.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits and its manufacture, in particular to a method for doping a body region of a MOS transistor. Background technique [0002] The main device in an integrated circuit, especially a VLSI, is a metal oxide semiconductor field effect transistor (MOSFET for short). Since the invention of the integrated circuit, its performance and function have progressed by leaps and bounds. And this progress is achieved simply by continuously shrinking the size of the device and increasing the chip area. The continuous shrinking of the device size has led to the continuous improvement of circuit performance and the continuous increase of circuit density, while the continuous expansion of chip size has prompted the continuous increase of circuit functions. Therefore, the geometric size of MOSFET has been continuously shrinking, and its characteristic size has entered the nanoscale at present....

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/266
Inventor 张盛东廖聪维孙雷陈文新韩汝琦
Owner SEMICON MFG INT (SHANGHAI) CORP
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