Adulation method for MOS transistor body area
A technology of MOS transistor and body region, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as reduced carrier mobility, increased parasitic capacitance and leakage current, and leakage parasitic resistance.
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[0040] Hereinafter, the best embodiment of the present invention will be described in more detail with reference to the accompanying drawings of the present invention.
[0041] (1) The substrate is a bulk silicon wafer
[0042] A specific example of the manufacturing method for preparing an integrated silicon MOS transistor is shown in FIG. 1 to FIG. 6, and includes the following steps:
[0043] 1) As shown in Figure 1, the crystal orientation of the single crystal silicon substrate used is (100). For n-type MOS transistors, body region 1 is initially lightly doped with p-type. For p-type MOS transistors, body region 1 is initially lightly doped n-type. The active area isolation layer 2 is fabricated using conventional CMOS shallow trench isolation technology. Then the gate dielectric layer 3 is grown. The gate dielectric layer 3 is silicon dioxide, and its thickness is 0.5-3 nm. The formation method of the gate dielectric can also be one of the following methods: conventional the...
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