30results about How to "Increase the electric field" patented technology

Disclosed are a method and apparatus that use an electric field for improved biological assays. The electric field is applied across a device having wells, which receive reactants, which carry a charge. The device thus uses a controllable voltage source between the first and second electrodes, which is controllable to provide a positive charge and a negative charge to a given electrode. By controlled use of the electric field charged species in a fluid in a fluid channel are directed into or out of the well by an electric field between the electrodes. The present method involves the transport of fluids, as in a microfluidic device, and the electric field-induced movement of reactive species according to various assay procedures, such as DNA sequencing, synthesis or the like.

An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.

In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

The invention discloses a packaging cover plate of a sensitivity-strengthened electric field sensor and a packaging method and relates to the technical field of electric field detection. The packaging cover plate comprises an inner core, a cover plate edge and an isolation ring, wherein the inner core is located in the middle of the cover plate and above the sensitive face of the packaged electric field sensor, and the sensitivity of the electric field sensor is effectively strengthened. The cover plate edge is used for connecting a packaging pipe housing. The isolation ring is located between the cover plate edge and the inner core to play supporting and isolation effects. In addition, the packaging convenience is further increased by adopting the structure. Correspondingly, the structure is successively prepared by adopting the packaging method of the corresponding electric field sensor.

The invention relates to the technical field of ceramics and functional decorative materials, and especially relates to a ceramic tile with a far infrared composite air purification function, and a preparation process thereof. The ceramic tile comprises a ceramic tile blank and a glaze layer, the glaze layer is prepared from far-infrared powder and negative ion powder, and the far-infrared powderis prepared from calcium oxide and nano-Y2O3-MgO far-infrared powder; the outer surface of the nano-Y2O3-MgO far infrared powder is wrapped by the negative ion powder and is sintered; the nano-Y2O3-MgO far infrared powder is adsorbed on the surfaces of the calcium oxide particles; the mixing ratio of the calcium oxide to the nano-Y2O3-MgO far infrared powder in parts by weight is 1: (3-4); and theweight part ratio of the far infrared powder to the negative ion powder is 1: (2-3). According to the ceramic tile with the far infrared composite air purification function, the activity of negativeion inducing substances in the negative ion powder can be activated, so more negative ions are induced to be generated for air purification.

The invention belongs to the logic device and circuit field in the super-large scale integrated circuit field and relates to a tunneling field effect transistor capable of increasing a current switching ratio. According to the tunneling field effect transistor, a low-K dielectric region is arranged between a source region and a drain region, so that an electric field between the source region and an intrinsic region can be increased, and therefore, on-state current can be improved, and off-state current can be suppressed; a doped layer is adopted, so that a reversely biased PN junction can be formed based on the substrate, and therefore, the contact of a source region-low-K dielectric region-drain region structure with the substrate can be isolated, and the off-state current of the tunneling field effect transistor (TFET) can be decreased. An on-state current increasing mode and an off-state current suppressing mode can be combined and overlapped with each other. Thus, the tunneling field effect transistor of the invention can improve the on-state current, is compatible with conventional CMOS technologies, is low in cost and can achieve a high current switching ratio.

An improved, low-cost system for mitigating electrostatic discharge (ESD) that may occur during egress from vehicles is provided. One embodiment comprises a narrow conductive electrode that is galvanically connected to the vehicle chassis, and that is applied to that one edge of a seat which is next to the door nearest that seat. For example, in the U.S., this edge will normally be the left edge of the driver's seat, or the right edge of the front passenger's seat. The electrode is substantially located on a normally unoccupied surface of the seat cushion. Other embodiments further include pointed shapes on the electrode to increase the electric field intensity, which may promote more complete discharging. Certain embodiments may allow a manufacturer to easily retrofit an existing seat design with an electrode by simply adding a manufacturing step. The system is simpler, less expensive, and more effective than prior art ESD mitigators.

The invention belongs to the field of a logic device and circuit in the field of a super-large-scale integrated circuit, specifically a tunnel field effect transistor with an increased on state current. According to the tunnel field effect transistor, a low K dielectric area is arranged between a source area and a drain area, thereby isolating the source area and the drain area; an intrinsic area is arranged on the source area; a layer of conductive channel is arranged between the intrinsic area and the drain area; and the conductive channel is located on the low K dielectric area. According to the structure of the tunnel field effect transistor, the bipolar effect of a traditional transverse TFET is weakened. Through utilization of a low K dielectric, the contact between the drain area and the intrinsic area is reduced and the bipolar effect is weakened, thereby facilitating thorough switch-off of a device. An electric field of a tunnel junction area is increased by employing the low K dielectric and a high K side wall. The on state current of the TFET is increased through adoption of the side wall (a passivation layer) made of a high dielectric material. According to the tunnel field effect transistor, the bipolar effect is weakened, the on state current is increased, the tunnel field effect transistor is compatible with a CMOS technology and the cost is low.

The invention provides a trench MOSFET and a manufacturing method thereof. The trench MOSFET comprises: a substrate having a first conductivity type; an epitaxial layer formed on the substrate and having a first conductivity type, the doping concentration of the epitaxial layer being lower than that of the substrate; a trench formed in the epitaxial layer; a buried layer formed below the trench and having a second conductivity type; a gate structure filled in the trench and comprising a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode and a dielectric layer which covers the shielding gate electrode and is filled in the side part of the control gate electrode; a body region having a second conductivity type and formed in the epitaxial layer; and a source region formed in the epitaxial layer, positioned above the body region and having a first conductivity type, the doping concentration of the source region being greater than that of the body region.

The invention discloses an integrated silicon carbide Darlington transistor and a manufacturing method thereof, and belongs to the technical field of micro-electronics, aiming at addressing the problems of small capability of driving tube current handling, complex manufacturing technologies, and high cost of current silicon carbide Darlington transistors. The integrated silicon carbide Darlington transistor includes: a N+emitting region which is arranged on the upper surface of a base region and includes a device slot which assumes the shape of a tilted slot, a device isolation region which assumes the shape of a vertical slot and an emitting region table which assumes the shape of a vertical slot; a base region P+ injection region which is arranged on a lower surface of the emitting region table and is disposed within the base region, wherein the device slot is arranged in the N+emitting region and extends to the upper portion of a N-collector region, the device isolation region is arranged in the N+emitting region and extends to the upper portion of the N-collector region; and an isolation injection layer which is arranged on the upper surface of the bottom portion of the device isolation region.

The present invention discloses a strip-shaped gate tunneling field effect transistor using composite mechanism and a fabrication method thereof, which belongs to a field of field effect transistor logic devices and circuits in the CMOS ultra large scale integrated circuit (ULSI). According to the tunneling field effect transistor, the energy band of the channel underneath the gate is elevated by means of a change of the gate morphology and the PN junction depletion effect occurred at both sides of the strip-shaped gate, so that the sub-threshold characteristics of the transistor are improved. Meanwhile, the on-state current of the transistor is effectively increased by means of the composite mechanism introduced by the two parts of the doped source region. Moreover, the bulk leakage current, including a source-to-drain direct tunneling current and a punching through current, which comes from the two parts of the doped source region to the doped drain region can be greatly suppressed through the design of the ‘’-shaped active region, so that the short channel effect is inhibited and thus the transistor can be applied with a smaller size.

A low-erosion radio frequency ion source is disclosed having a hollow body with conductive interior walls that define a cylindrical cavity, with a gas supply inlet for plasma-forming gases and a power supply inlet for injecting radio frequency energy into the cavity; an expansion chamber connected to the cavity by means of a plasma outlet hole; an ion-extraction aperture in contact with the expansion chamber; coaxial conductor disposed in the cavity, parallel to the longitudinal axis thereof, one or both ends of the coaxial conductor being in contact with a circular interior wall of the body, forming a coaxial resonant cavity; the coaxial conductor having a conductive protuberance opposite the plasma outlet hole and which extends radially into the cavity. It substantially reduces the erosion of the conductive materials.