Strip-shaped gate tunneling field effect transistor using composite mechanism and fabrication method thereof

Abstract

The present invention discloses a strip-shaped gate tunneling field effect transistor using composite mechanism and a fabrication method thereof, which belongs to a field of field effect transistor logic devices and circuits in the CMOS ultra large scale integrated circuit (ULSI). According to the tunneling field effect transistor, the energy band of the channel underneath the gate is elevated by means of a change of the gate morphology and the PN junction depletion effect occurred at both sides of the strip-shaped gate, so that the sub-threshold characteristics of the transistor are improved. Meanwhile, the on-state current of the transistor is effectively increased by means of the composite mechanism introduced by the two parts of the doped source region. Moreover, the bulk leakage current, including a source-to-drain direct tunneling current and a punching through current, which comes from the two parts of the doped source region to the doped drain region can be greatly suppressed through the design of the ‘’-shaped active region, so that the short channel effect is inhibited and thus the transistor can be applied with a smaller size.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority of Chinese Patent Application (No. 201310377553.4), filed on Aug. 27, 2013, which is incorporated herein by reference in its entirety.TECHNICAL FIELD[0002]The present invention belongs to a field of field effect transistor logic devices and circuits in the CMOS ultra large scale integrated circuit (ULSI), and particularly refers to a strip-shaped gate tunneling field effect transistor using composite mechanism and a fabrication method thereof.BACKGROUND OF THE INVENTION[0003]Driven by the Moore's Law, a feature size of the conventional MOSFET continues to shrink and now enters into a nanometer scale. Consequently, negative effects such as short channel effect become more serious. Besides, effects such as drain induced barrier lowering and band-to-band tunneling cause an off-state leakage current to be continually increased. At the same time, a sub-threshold slope of the conventional MOSFET is not ab...

AI Technical Summary

Benefits of technology

The present invention provides a strip-shaped gate tunneling field effect transistor (SFET) that uses a composite mechanism to achieve a steep source junction doping concentration, optimize the sub-threshold slope, and effectively suppress the source-to-drain direct tunneling current while maintaining a low leakage current. The SFET is fully compatible with the conventional CMOS process and can achieve a higher turn-on current and a steeper sub-threshold slope. The design of the SFET structure includes a strip-shaped gate, a "’’-shaped active region, and two parts of a doped source region. The SFET effectively modulates the tunneling junction in the source region, achieving a steeper energy band bending and a larger tunneling electric field, and improves the sub-threshold characteristics of the SFET. The SFET also suppresses the leakage current in case of short channel. The fabrication process of the SFET is simple, and the device can be used in the field of low power consumption.

Problems solved by technology

Consequently, negative effects such as short channel effect become more serious.

Besides, effects such as drain induced barrier lowering and band-to-band tunneling cause an off-state leakage current to be continually increased.

At the same time, a sub-threshold slope of the conventional MOSFET is not able to be decreased in synchronization with the shrink of the size of the MOSFET due to the limitation by the thermal potential, and thereby the power consumption increases.

The concern of the power consumption now becomes the most serious problem limiting the scaling down of the MOSFET.

However, due to the limitation of the tunneling probability and the tunneling area for the source junction, the TFET is faced with a problem of small on-state current, which is far less than that of the conventional MOSFET, and this greatly limits the application of the TFET.

In addition, the TFET having a steep sub-threshold slope is difficult to be achieved in experiments.

This is because it is difficult in experiments to achieve a steep doping concentration gradient at the source junction, so that the electric field at the tunneling junction is not sufficiently large when the TFET turns on, causing the sub-threshold slope of the TFET to be degraded relative to the theoretical value.

Therefore, it has become an important issue of the TFET that how to achieve a steep doping concentration gradient at the source junction in order to obtain an ultra-low sub-threshold slope while obtaining a high on-state current.

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