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Integrated silicon carbide Darlington transistor and manufacturing method thereof

A Darlington tube, integrated technology, applied in the field of microelectronics, can solve the problems of complex manufacturing process, small current handling capacity of the drive tube, and high cost

Active Publication Date: 2017-04-26
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] To sum up, the existing silicon carbide Darlington tube has the problem of relatively small current handling capacity of the drive tube and complicated manufacturing process, resulting in relatively high cost.

Method used

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  • Integrated silicon carbide Darlington transistor and manufacturing method thereof
  • Integrated silicon carbide Darlington transistor and manufacturing method thereof
  • Integrated silicon carbide Darlington transistor and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] In the first step, the N+ buffer layer 102 is epitaxially grown on the N+ substrate 101 . Specifically, such as Figure 2A As shown, the N+ substrate 101 is firstly cleaned by RCA standard; and then epitaxially grown on the front surface of the N+ substrate 101 with a low-pressure hot-wall chemical vapor deposition method with a thickness of 3.5 μm and a nitrogen ion doping concentration of 8×10 17 cm -3 N+ buffer layer 102.

[0051] It should be noted that the growth conditions of the N+ buffer layer 102 are as follows: the temperature is 1600° C., the pressure is 100 mbar, the reaction gas includes silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0052] It should be noted that the RCA standard cleaning method was first created by Kern and Puotinen in the RCA laboratory of N.J.Princeton in 1965, and thus got its name. RCA is a typical wet chemical cleaning method that is still the most commonly used. The cleaning me...

Embodiment 2

[0087] In step 1, an N+ buffer layer 102 is epitaxially grown on the N+ substrate 101 . Specifically, such as Figure 2A As shown, the N+ type silicon carbide substrate 10 is firstly cleaned by RCA standard; then, the epitaxial growth thickness is 5 μm and the nitrogen ion doping concentration is 1×10 18 cm -3 The buffer layer 102.

[0088] It should be noted that the growth conditions of the N+ buffer layer 102 are as follows: the temperature is 1600° C., the pressure is 100 mbar, the reaction gas includes silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0089] Step 2, epitaxially growing the N- collector region 103 on the N+ buffer layer 102, specifically, as Figure 2B As shown, the buffer layer 102 is epitaxially grown on the buffer layer 102 with a thickness of 100 μm and a doping concentration of nitrogen ions of 2×10 14 cm -3 N-collector region 103 .

[0090] It should be noted that the growth process conditions o...

Embodiment 3

[0116] In step A, the N+ buffer layer 102 is epitaxially grown on the N+ substrate 101 . Specifically, such as Figure 2AAs shown, the N+ type silicon carbide substrate 10 is firstly cleaned by RCA standard; and then epitaxially grown on the front surface with a thickness of 6 μm and a nitrogen ion doping concentration of 5×10 18 cm -3 The buffer layer 102.

[0117] It should be noted that the growth conditions of the N+ buffer layer 102 are as follows: the temperature is 1600° C., the pressure is 100 mbar, the reaction gas includes silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0118] Step B, epitaxially growing the N- collector region 103 on the N+ buffer layer 102, specifically, as Figure 2B As shown, the buffer layer 102 is epitaxially grown on the buffer layer 102 by the low-pressure hot-wall chemical vapor deposition method with a thickness of 105 μm and a nitrogen ion doping concentration of 6×10 14 cm -3 N-coll...

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Abstract

The invention discloses an integrated silicon carbide Darlington transistor and a manufacturing method thereof, and belongs to the technical field of micro-electronics, aiming at addressing the problems of small capability of driving tube current handling, complex manufacturing technologies, and high cost of current silicon carbide Darlington transistors. The integrated silicon carbide Darlington transistor includes: a N+emitting region which is arranged on the upper surface of a base region and includes a device slot which assumes the shape of a tilted slot, a device isolation region which assumes the shape of a vertical slot and an emitting region table which assumes the shape of a vertical slot; a base region P+ injection region which is arranged on a lower surface of the emitting region table and is disposed within the base region, wherein the device slot is arranged in the N+emitting region and extends to the upper portion of a N-collector region, the device isolation region is arranged in the N+emitting region and extends to the upper portion of the N-collector region; and an isolation injection layer which is arranged on the upper surface of the bottom portion of the device isolation region.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to a semiconductor device, in particular to an integral silicon carbide Darlington tube and a manufacturing method thereof. Background technique [0002] With the rapid development of power electronics technology, the demand for high-power semiconductor devices is becoming more and more significant. Due to the limitation of materials, the characteristics of traditional silicon devices have reached its theoretical limit. Silicon carbide is a wide bandgap semiconductor material that has been developed rapidly in the past ten years. It has wide bandgap, high thermal conductivity, and high carrier saturation migration. High efficiency, high power density and other advantages, can be applied to high power, high temperature and radiation resistance and other application fields. Among them, the oxide layer-based MOSFET (English: Metal-Oxide-Semiconductor Field-Effect Transistor, Ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/082H01L29/08H01L21/8222
Inventor 元磊李钊君宋庆文汤晓燕张艺蒙张玉明
Owner XIDIAN UNIV
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