Tunnel field effect transistor with increased on state current

Abstract

The invention belongs to the field of a logic device and circuit in the field of a super-large-scale integrated circuit, specifically a tunnel field effect transistor with an increased on state current. According to the tunnel field effect transistor, a low K dielectric area is arranged between a source area and a drain area, thereby isolating the source area and the drain area; an intrinsic area is arranged on the source area; a layer of conductive channel is arranged between the intrinsic area and the drain area; and the conductive channel is located on the low K dielectric area. According to the structure of the tunnel field effect transistor, the bipolar effect of a traditional transverse TFET is weakened. Through utilization of a low K dielectric, the contact between the drain area and the intrinsic area is reduced and the bipolar effect is weakened, thereby facilitating thorough switch-off of a device. An electric field of a tunnel junction area is increased by employing the low K dielectric and a high K side wall. The on state current of the TFET is increased through adoption of the side wall (a passivation layer) made of a high dielectric material. According to the tunnel field effect transistor, the bipolar effect is weakened, the on state current is increased, the tunnel field effect transistor is compatible with a CMOS technology and the cost is low.

Description

technical field [0001] The invention belongs to the field of logic devices and circuits in the field of ultra-large-scale integrated circuits, and relates to a longitudinal tunneling TFET device with small size and increased on-state current, in particular to a tunneling field-effect transistor with increased on-state current. Background technique [0002] With the advancement of lithography, implantation and other process technologies, the integration of chips is getting higher and higher, and the power consumption density is also increasing; moreover, the feature size of MOSFET devices is getting smaller and smaller, and the short channel effect, GIDL (gate induced Drain leakage current) becomes severe, further increasing the off-state current. Therefore, the solution to the power consumption problem directly affects the improvement of chip integration. [0003] Finding a device structure with small leakage is the most direct way to solve the static power consumption prob...

AI Technical Summary

Problems solved by technology

The source region 1 material is GaAs 0.4 Sb 0.6 , the material of intrinsic region 2 and drain region 3 is In 0.65 Ga 0.35 As, at this time, the substrate generally requires a III-V compound semiconductor buffer layer, resulting in the incompatibility of this type of device fabrication with the traditional CMOS process line, and the cost is very high

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