Semiconductor packaging member and method for fabricating the same

Abstract

The invention relates to an encapsulation piece of a semiconductor and a manufacturing method thereof. The method essentially includes the following steps: a sacrificial layer is laid between a metallic carrier tool and an insulating layer, and preconcerted parts of the sacrificial layer and the insulating layer are opened with a plurality of perforative openings, so that a conductive metal layer can be generated in the openings subsequently and a patterned line layer can be generated on the insulating layer subsequently, and the patterned line layer is electrically connected with the conductive metal layer; then at least one chip is electrically connected with the patterned line layer and an encapsulated colloid which wraps the chip and the patterned line layer, in other words, the metallic carrier tool and the sacrificial layer are removed, so that the conductive metal layer generated formerly to prong the sacrificial layer and the opening of the insulating layer is relatively protruded when compared with the insulating layer; in this way, when the completed encapsulation piece of the semiconductor is electrically connected with outer devices, a distance between the encapsulation piece of the semiconductor and the outer devices can be increased, as a result, thermal stress generated by difference of thermal expansion coefficient between the encapsulation piece of the semiconductor and the outer devices can be reduced, and the reliability is improved.

Description

technical field [0001] The invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package that does not need a carrier and its manufacturing method. Background technique [0002] Traditional semiconductor chips use a lead frame as a chip carrier to form a semiconductor package. The welding frame includes a chip holder and a plurality of leads formed around the chip holder. After the semiconductor chip is bonded to the chip holder and the chip and the leads are electrically connected by welding wires, the chip is covered by encapsulation resin, The chip base, the bonding wire and the inner section of the lead form the semiconductor package with the soldering frame. [0003] There are many types and types of semiconductor packages with soldering frames as chip carriers. As far as the quad flat non-leaded (QFN) semiconductor package is concerned, it is characterized in that no external leads are provided. That is, there is ...

AI Technical Summary

Problems solved by technology

Therefore, in the aforementioned existing semiconductor package, due to the extremely low height of the solder joint, a great thermal stress will be generated on the solder joint between the semiconductor package and the printed circuit board, which not only causes the semiconductor package The fatigue life of the solder joints with the printed circuit board is reduced, which will even cause cracks in the solder joints, seriously affecting the reliability of electronic products; relatively, if the setting and height of the solder volume are increased, Also, due to the excessive amount of solder, or poor control of the contact distance between the package and the printed circuit board, the adjacent solder material contacts and a short circuit occurs, which leads to troubles in the manufacturing method.

[0010] Therefore, how to solve the above problems and provide a semiconductor package without a carrier and its manufacturing method, avoid cracks and poor reliability of solder joints, and flexibly arrange circuits to effectively shorten the welding line Arc length, so as to improve the circuit layout and electrical connection quality, it is urgent

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