Grids production method

A manufacturing method and gate technology, which are used in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., to achieve the effects of improving efficiency, improving reliability, and reducing costs
CN101197262AInactive Publication Date: 2008-06-11SEMICON MFG INT (SHANGHAI) CORP +1

Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2008-06-11
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention relates to a manufacture method for grid, which comprises the following steps of: providing a semi-conductor substrate and forming a conductive layer on the semi-conductor substrate; revolving and coating optical carved glue layer on the conductive layer and imaging to form a grid pattern; transferring the grid pattern to the conductive layer through etching; measuring the line width of the grid and judging whether the bottom of the grid has a foot-shaped drawback, and performing directional plasma etching for the grid which has the foot-shaped drawback. The grid formed by the method has a better side wall profile.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate in a semiconductor device. Background technique

[0002] With the advancement of semiconductor manufacturing technology, the size of its gate is getting smaller and smaller, and the small gate line width can reduce the driving voltage of the formed device, thereby reducing power consumption; at the same time, it can reduce the size of the entire device formed Therefore, the industry always forms a smaller gate size through various methods. In the Chinese patent application number 200410093459, a process for reducing the gate line width is disclosed. Figure 1 to Figure 5 A schematic cross-sectional view of a structure corresponding to the process disclosed in said patent.

[0003] Such as figure 1 As shown, a semiconductor substrate 100 is first provided, a gate oxide layer 102 is formed on the semiconductor substrate 100, ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
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