Method for making double-metal inlaid structure
A technology of metal inlay and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc. It can solve problems such as rounding of the corners of trenches 110, damage, and electrical problems of components, and achieve the effect of preventing bridging
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Embodiment 1
[0050] Figure 3A to Figure 3F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to an embodiment of the present invention.
[0051] Please refer to Figure 3A , the dual damascene structure of this embodiment is formed on the substrate 200 . A conductive layer 202 has been formed on the substrate 200 and covered with a liner layer 204 . The substrate 200 is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The liner 204 covering the conductor layer 202 can prevent the conductor layer 202 from being oxidized, and its material is, for example, silicon nitride. A dielectric layer 206 is formed on the liner 204 , and its material is, for example, a low dielectric constant material with a dielectric constant lower than 4. Next, a metal hard mask layer 210 is formed on ...
Embodiment 2
[0060] Figure 5A to Figure 5F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to another embodiment of the present invention. Embodiment 2 is similar to Embodiment 1, but after forming the low dielectric constant material layer and before forming the metal hard mask layer, a top layer is first formed on the low dielectric constant material layer as a subsequent chemical mechanical polishing process grinding stop layer.
[0061] Please refer to Figure 5A , providing a substrate 200 on which a conductor layer 202 has been formed and a liner layer 204 has been covered on the conductor layer 202 . The substrate 200 is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The lining layer 204 covering the conductor layer 202 can prevent the conductor layer 202 from being...
Embodiment 3
[0068] Figure 6A to Figure 6F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to another embodiment of the present invention. Embodiment 3 is similar to Embodiment 1, but after forming the metal hard mask layer and before forming the anti-reflection layer, a top cover layer is first formed on the metal hard mask layer to avoid subsequent removal of the exposed area of the dielectric layer window opening. When the liner is used, the pollution problem caused by the exposed metal hard mask layer.
[0069] Please refer to Figure 6A, providing a substrate 200 on which a conductive layer 202 is formed and covered with a liner 204 , which is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The lining layer 204 covering the conductor layer 202 can prevent the conducto...
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Abstract
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