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Method for making double-metal inlaid structure

A technology of metal inlay and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc. It can solve problems such as rounding of the corners of trenches 110, damage, and electrical problems of components, and achieve the effect of preventing bridging

Active Publication Date: 2012-04-18
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Please refer to Figure 1A-1B During the etching process of the trench 110, the liner layer 104 exposed by the dielectric layer window opening 108 will also be damaged by the etchant, so that the metal layer 102 is exposed, causing electrical problems in the device
In addition, during the etching process, the silicon nitride layer 107 and the underlying dielectric layer 106 are also easily damaged by the etchant, so that the top corner of the trench 110 is rounded.

Method used

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  • Method for making double-metal inlaid structure
  • Method for making double-metal inlaid structure
  • Method for making double-metal inlaid structure

Examples

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Embodiment 1

[0050] Figure 3A to Figure 3F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to an embodiment of the present invention.

[0051] Please refer to Figure 3A , the dual damascene structure of this embodiment is formed on the substrate 200 . A conductive layer 202 has been formed on the substrate 200 and covered with a liner layer 204 . The substrate 200 is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The liner 204 covering the conductor layer 202 can prevent the conductor layer 202 from being oxidized, and its material is, for example, silicon nitride. A dielectric layer 206 is formed on the liner 204 , and its material is, for example, a low dielectric constant material with a dielectric constant lower than 4. Next, a metal hard mask layer 210 is formed on ...

Embodiment 2

[0060] Figure 5A to Figure 5F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to another embodiment of the present invention. Embodiment 2 is similar to Embodiment 1, but after forming the low dielectric constant material layer and before forming the metal hard mask layer, a top layer is first formed on the low dielectric constant material layer as a subsequent chemical mechanical polishing process grinding stop layer.

[0061] Please refer to Figure 5A , providing a substrate 200 on which a conductor layer 202 has been formed and a liner layer 204 has been covered on the conductor layer 202 . The substrate 200 is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The lining layer 204 covering the conductor layer 202 can prevent the conductor layer 202 from being...

Embodiment 3

[0068] Figure 6A to Figure 6F It is a schematic cross-sectional view of a method for manufacturing a dual damascene structure according to another embodiment of the present invention. Embodiment 3 is similar to Embodiment 1, but after forming the metal hard mask layer and before forming the anti-reflection layer, a top cover layer is first formed on the metal hard mask layer to avoid subsequent removal of the exposed area of ​​the dielectric layer window opening. When the liner is used, the pollution problem caused by the exposed metal hard mask layer.

[0069] Please refer to Figure 6A, providing a substrate 200 on which a conductive layer 202 is formed and covered with a liner 204 , which is, for example, a semiconductor substrate, such as a silicon substrate or a silicon substrate on an insulating layer. The conductor layer 202 is, for example, a metal interconnection, such as a copper wire. The lining layer 204 covering the conductor layer 202 can prevent the conducto...

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Abstract

The invention discloses a method to fabricate a dual metal mosaic structure. A dielectric layer and a metal mask layer are sequentially developed on a substrate which is provided with a conductive layer and an underlayer; the substrate is patterned, and a window for the dielectric layer is formed, exposed outside the underlayer; then a packing layer is filled in the window of the dielectric layer, and the height of the packing layer is between one forth and a half of the depth of the window of the dielectric layer, then a groove is fashioned between the metal mask layer and the dielectric layer; after that, the packing layer is removed and the underlayer exposed outside the window of the dielectric layer is etched, with the metal mask layer as the mask; finally, metal layers are developedin the window of the dielectric layer and in the groove, and the metal mask layer is removed.

Description

technical field [0001] The invention relates to a method for manufacturing a metal interconnection, and in particular to a method for manufacturing a double metal damascene structure. Background technique [0002] With the improvement of the integration level of semiconductor devices, the use of multiple metal interconnections is becoming more and more extensive. Generally, the lower the resistance value of the metal layer of the multi-metal interconnection, the higher the reliability of the device and the better the performance. Among metal materials, copper metal has a low resistance value and is very suitable for multi-metal interconnection. However, because copper metal is difficult to pattern by traditional photolithography and etching technology, a process called dual damascene has been developed. [0003] The dual damascene process is a technique of forming trenches and openings of dielectric windows in the dielectric layer, and then backfilling metal to form metal w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 张光晔马宏
Owner UNITED MICROELECTRONICS CORP
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