Heterostructure field effect transistor and manufature method thereof
A field-effect transistor and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the study of no AlN layer, and achieve suppression of cracks in the AlN layer, suppression of short-channel effects, and reduction of The effect of thickness
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no. 1 Embodiment approach
[0051] A heterojunction field effect transistor according to a first embodiment will be described with reference to FIG. 1 . In addition, since this heterojunction field effect transistor is a high electron mobility transistor (HEMT), it may also be called HEMT in the following description.
[0052] FIG. 1 is a schematic diagram for explaining a heterojunction field effect transistor according to a first embodiment, showing cutaway end faces of main parts.
[0053] The heterojunction field effect transistor 10 according to the first embodiment is configured to include a laminate 30 in which a first GaN layer as a channel layer 40 and a GaN layer as an electron supply layer 50 are sequentially laminated on a substrate 20 . AlN layer, and the second GaN layer as the cladding layer 60 . A two-dimensional electron gas (2DEG) is formed on the interface between the first GaN layer as the channel layer 40 and the AlN layer as the electron supply layer 50 , that is, the AlN / GaN-heter...
no. 2 Embodiment approach
[0080] A heterojunction field effect transistor according to the second embodiment will be described with reference to FIG. 7 . 7 is a schematic diagram illustrating a heterojunction field effect transistor according to a second embodiment, showing cutaway end faces of main parts.
[0081] The heterojunction field effect transistor 11 of the second embodiment is a field effect transistor (MISFET) of a so-called MIS (Metal Insulator Semiconductor: Metal Insulator Semiconductor) structure. A silicon nitride film at 92 has a gate electrode 80 on the gate insulating film 92 .
[0082] By adopting the MIS structure, gate leakage current can be suppressed. Even in the case of laminating a silicon nitride film with a thickness of 14 nm as the gate insulating film, as long as the thickness of the electron supply layer is 2.4 nm and the thickness of the capping layer is 3.3 nm, the thickness a of the active layer is 20 nm or less. Even when the pole length is 100 nm, an aspect ratio ...
no. 3 Embodiment approach
[0092] A heterojunction field effect transistor according to a third embodiment will be described with reference to FIG. 10 . FIG. 10 is a schematic diagram illustrating a heterojunction field effect transistor according to a third embodiment, showing cutaway end faces of main parts.
[0093] The heterojunction field effect transistor 12 of the third embodiment is configured to include a laminate 32 in which a GaN layer serving as a channel layer 40 and an AlN layer serving as an electron supply layer 50 are laminated in this order. A two-dimensional electron gas (2DEG) is formed at the AlN / GaN-heterointerface between the GaN layer as the channel layer and the AlN layer as the electron supply layer.
[0094] A silicon nitride film serving as a gate insulating film 92 is formed on the electron supply layer. As in the second embodiment, a GaN layer and an AlN layer are formed by MOCVD, and after forming an AlN layer as an electron supply layer, a silicon nitride film is formed ...
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