Read operation for non-volatile storage with compensation for floating gate coupling

A technology of non-volatile storage and memory, applied in the field of non-volatile memory

Active Publication Date: 2009-03-25
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Various embodiments are disclosed

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  • Read operation for non-volatile storage with compensation for floating gate coupling
  • Read operation for non-volatile storage with compensation for floating gate coupling
  • Read operation for non-volatile storage with compensation for floating gate coupling

Examples

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Embodiment Construction

[0042] One example of a memory system suitable for implementing the invention uses a NAND flash memory structure that includes arranging multiple transistors in series between two select gates. The series connection of transistors and select gates is called a NAND string. figure 1 is a top view showing a NAND string. figure 2 is its equivalent circuit. figure 1 and 2The depicted NAND string includes four transistors 100 , 102 , 104 and 106 connected in series and sandwiched between a first select gate 120 and a second select gate 122 . Select gate 120 gates the NAND string connection to bit line 126 . Select gate 122 gates the NAND string connection to source line 128 . Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG. Select gate 122 is controlled by applying an appropriate voltage to control gate 122CG. Each of transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG a...

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Abstract

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. For this, a read voltage is applied to the word line of the selected memory cell, a second pass voltage is applied to the word line of the memory cell adjacent to the selected memory cell and a first pass voltage is applied to the further word lines. Before reading the selected memory cell, the state of the adjacent memory cell is read and, according to this state, the second pass voltage is set.

Description

technical field [0001] The present invention relates to techniques for non-volatile memory. Background technique [0002] Semiconductor memories have been increasingly used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are the most common non-volatile semiconductor memories. [0003] Both EEPROM and flash memory utilize a floating gate positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between a source region and a drain region. A control gate is provided over and insulated from the floating gate. The threshold voltage of a transistor is controlled by the amount of charge retained on the floating gate. That is, the minimum amount of voltage that mus...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26
CPCG11C16/3418G11C16/26G11C11/5628G11C11/5642G11C16/0483G11C16/08G11C16/3459
Inventor 尼玛·穆赫莱斯
Owner SANDISK TECH LLC
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