Plane double diffusion metal oxide semiconductor device and preparation method

Abstract

The invention discloses a planar double-diffused metal oxide semiconductor device and a manufacturing method thereof, which aim to reduce on-resistance of a junction type field effect transistor of the planar double-diffused metal oxide semiconductor device and to increase the performance of the planar double-diffused metal oxide semiconductor. Before manufacturing a Planar DMOS device, the technical scheme includes implanting first doping atoms into the surface layer of a wafer epitaxial layer with doping concentration higher than that of another part of the epitaxial layer, driving the first doping atoms into the epitaxial layer for reducing resistivity of certain depth of the wafer epitaxial layer, thereby reducing the width of a deletion layer, widening the current passage, reducing the on-resistance of the junction type field effect transistor, further reducing the on-resistance and improving the performance of the planar double-diffused metal oxide semiconductor device.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a manufacturing technology of a planar double diffused metal oxide semiconductor device. Background technique [0002] Double diffused MOS (DMOS) is a type of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which uses diffusion to form its transistor area. Double-diffused transistors are usually used as power transistors in high-voltage power integrated circuits, and provide higher current per unit area under the requirement of low forward voltage drop. [0003] One type of double diffused transistor is Planar DMOS (Planar Double-diffused MetalOxide Semiconductor), such as figure 1 As shown, in the PlanarDMOS process, Rdson=Rch+Ra+Rjfet+Repi+Rsub+Rc. Among them, Rdson is the on-resistance (static drain-source on-resistance), Rch is the channel resistance (channel resistance), Ra is the accumulation resistance (accumulate resistance), Rjfet is the junction f...

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Problems solved by technology

[0004] The existing process of manufacturing Planar DMOS is to directly manufacture Planar DMOS devices on the epitaxial layer of the wafer. Using this manufacturing method to manufacture Planar DMOS devices, the width of the depletion layer (width1) of the die is compared when the die is turned on. Large, the current channel "neck" (width2) is relatively narrow, so that the resistivity of the "neck" is relatively high, so Rjfet is relatively large, which in turn leads to a large Rdson of the Planar DMOS device, which affects the performance of the Planar DMOS device

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