Encoder convenient for LDPC long code implementation on FPGA and encoding method
An encoder and encoding technology, which is applied in the application of error detection coding with multiple parity bits, error correction/detection using convolutional codes, error correction/detection using block codes, etc., can solve the problem of LDPC check matrix Problems such as complexity, difficulty in implementation and popularization, etc., to achieve the effect of low design complexity, high reliability, and simple implementation
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[0067] The input of the LDPC encoder is 20M clock, 16-bit wide data, the lowest bit is the first input to-be-encoded data symbol, the to-be-encoded data is input in the unit of the LDPC to-be-encoded block, and fifteen complete blocks are continuously input for each encoding. For 1 / 2 code rate (4608 is an LDPC code block), the input data length is 15*4608 / 16=4320 (word); for 3 / 4 code rate (6912 is an LDPC code block), The input data length is 15*6912 / 16=6480(word); the implementation process description, taking 1 / 2 code rate as an example, each LDPC data block to be encoded has 15*4608 bits, and the ping-pong buffer module is grouped into input modules. 4608-bit packets are received. When the first packet has been received, switch to another input buffer to continue to receive data. The ping-pong buffer module groups the input module, and outputs 128 bits in parallel according to the encoding rate requirements for encoding. The encoding operation part adopts 80MHz. The system ...
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