Encoder convenient for LDPC long code implementation on FPGA and encoding method

An encoder and encoding technology, which is applied in the application of error detection coding with multiple parity bits, error correction/detection using convolutional codes, error correction/detection using block codes, etc., can solve the problem of LDPC check matrix Problems such as complexity, difficulty in implementation and popularization, etc., to achieve the effect of low design complexity, high reliability, and simple implementation

Active Publication Date: 2009-07-22
SPACE STAR TECH CO LTD
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Problems solved by technology

[0006] The Chinese patent "A Channel Coding and Interleaving Method in Mobile Multimedia Broadcasting" (Patent No. 200610149782.0) provides some algorithmic descriptions of the advantages of the LDPC algorithm in the communication field and some descriptions related to t

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  • Encoder convenient for LDPC long code implementation on FPGA and encoding method
  • Encoder convenient for LDPC long code implementation on FPGA and encoding method
  • Encoder convenient for LDPC long code implementation on FPGA and encoding method

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[0067] The input of the LDPC encoder is 20M clock, 16-bit wide data, the lowest bit is the first input to-be-encoded data symbol, the to-be-encoded data is input in the unit of the LDPC to-be-encoded block, and fifteen complete blocks are continuously input for each encoding. For 1 / 2 code rate (4608 is an LDPC code block), the input data length is 15*4608 / 16=4320 (word); for 3 / 4 code rate (6912 is an LDPC code block), The input data length is 15*6912 / 16=6480(word); the implementation process description, taking 1 / 2 code rate as an example, each LDPC data block to be encoded has 15*4608 bits, and the ping-pong buffer module is grouped into input modules. 4608-bit packets are received. When the first packet has been received, switch to another input buffer to continue to receive data. The ping-pong buffer module groups the input module, and outputs 128 bits in parallel according to the encoding rate requirements for encoding. The encoding operation part adopts 80MHz. The system ...

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Abstract

The invention relates to a coder for conveniently implementing a LDPC long code in an FPGA and a coding method. A LDPC coding module receives uncoded data output from a ping-pong buffer group input module and a check matrix output from a Synchronous Dynamic Random Access Memory (SDRAM) check matrix group module, obtains a parity matrix check code after a coding operation, outputs the code to a coding output buffer module for a code rate match, transmits the matched parity matrix check code with a certain length to an interleaving module in the LDPC for a bit combination and a bit interleave and outputs the interleaved coding data. The technical scheme of the invention has advantages of less hardware source, low design complexity, high operation frequency, easy implementation and high reliability, and flexibly implements different application environment demands according to the actual utilization demands and the hardware source conditions.

Description

technical field [0001] The invention relates to the field of satellite digital multimedia broadcasting, in particular to an encoder and an encoding method that facilitate the realization of LDPC long codes in FPGA. Background technique [0002] Digital broadcasting has the characteristics of wide coverage and large signal capacity. Therefore, as an important part of the information and communication industry, it plays an important role in the construction of national information infrastructure, the realization of universal services and the national information security strategy. [0003] In broadcast channel transmission, the transmission medium and other signal sources will introduce a series of influences to the signal, and the signal will experience fading, distortion and interference, etc., resulting in bit errors. Through channel coding and interleaving, the bit error rate can be greatly reduced. [0004] In the current mobile multimedia broadcasting system, the video s...

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Application Information

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IPC IPC(8): H04N7/26H03M13/11H03M13/23H04N19/88
Inventor 叶南生邹光南王海涛
Owner SPACE STAR TECH CO LTD
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