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Hardware design structure of overtime timer in communication protocol processor

A communication protocol and hardware design technology, applied in the direction of generating/distributing signals, etc., can solve the problems that affect the performance of the protocol processor, the accuracy of the timeout timer is not high, and the working speed is slow, and achieve performance improvement, efficiency improvement, and high precision. Effect

Inactive Publication Date: 2010-09-15
PEKING UNIV
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Problems solved by technology

[0003] In order to solve the above-mentioned problem that the accuracy of the timeout timer is not high and the working speed is slow, which affects the performance of the protocol processor, the invention provides a hardware design structure of the timeout timer in the communication protocol processor

Method used

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  • Hardware design structure of overtime timer in communication protocol processor
  • Hardware design structure of overtime timer in communication protocol processor
  • Hardware design structure of overtime timer in communication protocol processor

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Embodiment Construction

[0017] The specific implementation of the hardware design structure of the timeout timer in a communication protocol processor of the present invention will be described below in conjunction with the accompanying drawings.

[0018] figure 1 It is a schematic diagram of the hardware design structure of the overtime timer in a communication protocol processor of the present invention. The design structure of the present invention includes a control logic module 1, a timer module 2, a multiplexer 3, a comparator module 4, or a logic module 5 , timeout table module 7 and filter 6, in this structure, the calculation of the timeout time is completed by the control logic module 1 in the work, and relevant information including keywords and timeout time of the identification table item are written into the timeout time of the timeout table module 7 Table entry, during the working process, the content of the timeout entry will continue to change, such as inserting a new entry, deleting...

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Abstract

The invention discloses a hardware design structure of an overtime timer in a communication protocol processor, and relates to the technical field of protocol processor design. The hardware design structure mainly aims to solve the problems that the performance of the protocol processor is influenced due to the not-high precision and low working speed of the overtime timer in the conventional communication protocol processor. The hardware design structure of the invention comprises a control logic module, a timer module, a multi-path selector, a comparator module, or a logic module, an overtime table module and a filter. In the hardware design structure, software is replaced by a hardware structure to perform the searching, deleting and inserting operation of overtime table items, so that the performance of the overtime timer is greatly improved; and at the same time, the precision of the hardware timer is not limited by the highest frequency of an embedded processor by setting the timers with different precisions, so that higher precision can be achieved.

Description

technical field [0001] The invention belongs to the technical field of protocol processor design, in particular to a hardware design structure of an overtime timer in a communication protocol processor. Background technique [0002] The protocol processor mainly implements the function of processing certain communication protocols (such as Bluetooth protocol, USB protocol, etc.). The general data flow model in the protocol processor includes physical layer, link layer, network layer, transport layer and application layer. . In the processing of the communication protocol, an essential functional module is the overtime timing functional module. Timeout timing means that every time a frame of data is sent, it needs to start timing, and stop timing when the response frame of the data frame is received. If the response frame has not been received within the time specified by the timer, it means that the sent data frame is lost or the response frame is lost, and the data frame ...

Claims

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Application Information

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IPC IPC(8): G06F1/14
Inventor 金婕于敦山崔小欣王阳元
Owner PEKING UNIV
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