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Quick locking control circuit of pulse width control loop

A fast locking, pulse width control technology, applied in pulse duration/width modulation, pulse shaping and other directions, can solve the problems of low-precision A/D converter, increased system power consumption, occupying layout area, etc., to achieve a simple circuit structure , the locking time is shortened, and the layout area is very large.

Inactive Publication Date: 2012-02-22
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this circuit is that it needs to design an additional low-precision A / D converter and current mirror array, which takes up a lot of layout area and increases the power consumption of the system

Method used

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  • Quick locking control circuit of pulse width control loop
  • Quick locking control circuit of pulse width control loop
  • Quick locking control circuit of pulse width control loop

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Experimental program
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Embodiment Construction

[0025] The specific implementation manners of the present invention are not limited to the following description, and are now further described in conjunction with the accompanying drawings.

[0026] The circuit diagram of the fast locking control circuit of the pulse width control loop implemented by the present invention is as follows: figure 2 shown. It consists of a conventional inverter Q with an enable terminal 1 , a conventional inverter Q 2 , a conventional D-type flip-flop Q with a reset terminal 3 , conventional PMOS tube PM 1 , conventional NMOS tube NM 1 and the conventional resistor R 1 , R 2 composition.

[0027] figure 2 The specific connection in is the same as the content of the invention in this specification, and will not be repeated here. It works like this:

[0028] The input port of the circuit of the present invention is the input clock clk and the output clock terminal clk_out of the pulse width control loop system. The circuit output port ...

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PUM

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Abstract

The invention relates to a quick locking control circuit of a pulse width control loop, comprising a phase inverter Q1 with an enabling end, a phase inverter Q2, a D-type trigger Q3 with an asynchronous zero-clearing end, a PMOS (P-channel Metal Oxide semiconductor) transistor PM1, an NMOS (N-channel Metal Oxide semiconductor) transistor NM1 and resistors R1 and R2. The circuit has simple structure and can ensure that the locking time of a pulse width control system is greatly reduced and the amplitude thereof is reduced by more than seven times. The circuit can ensure that the pulse width control loop system automatically resets when stopping by accident and the pulse width control loop system enters into a power saving mode after working normally and has very little power consumption and high reliability. The circuit is suitable for the pulse width control loop system with a charge pump.

Description

technical field [0001] The invention relates to a time fast locking control circuit, in particular to a pulse width control loop fast locking control circuit. Its direct application field is the clock pulse width control loop system in high-speed high-precision analog-to-digital converters. Background technique [0002] In recent years, systems such as DDR SDRAM and A / D converters have adopted double-rate technology (DDR) to meet people's requirements for high-speed processing. In these systems, not only is the clock duty cycle accurate to 50%, but the circuit is also required to have a fast locking duty cycle. [0003] The pulse width control loop system can well solve the requirements of high-speed operation and precise locking. In order to obtain accurate control voltage to achieve precise locking and small peak-to-peak jitter, a low loop gain is required. However, low loop gain will bring a very long locking time, and the unlocked time period will affect the normal ope...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K7/08H03K5/04
Inventor 徐鸣远李婷李梁李儒章陈光炳
Owner NO 24 RES INST OF CETC