Method for preparing groove-type double-layer gate power metal oxide semiconductor (MOS) transistor

Abstract

The invention discloses a method for preparing a groove-type double-layer gate power metal oxide semiconductor (MOS) transistor, which comprises the following steps after a first layer of polysilicon in a groove is etched to a preset depth and before a second layer of polysilicon is deposited: 1, removing oxides on the side wall and the silicon plane of the groove; 2, carrying out nitrogen ion injection process so as to inject nitrogen ions to the side wall of the groove; and 3, carrying out thermal oxidation process so as to form silicon oxide on the side wall of the groove and on the surface of the first layer of polysilicon. Due to injection of the nitrogen ions on the side wall, the forming speed of an oxide layer is reduced. The oxide layer formed between the two layers of polysilicon by the method disclosed by the invention has uniform thickness and is thicker than a gate oxide layer between the side wall and the second layer of polysilicon, so that the performance of a device is obviously improved. Meanwhile, the oxide layers at two different positions are formed by the same process, so that the process is easy to control.

Description

technical field [0001] The invention relates to a preparation method of a MOS transistor, in particular to a preparation method of a trench type double-layer gate power MOS transistor. Background technique [0002] Among power devices, trench double-layer gate power MOS devices have the characteristics of high breakdown voltage, low on-resistance, and fast switching speed. Usually, the first layer of polysilicon is short-circuited with the source or drawn out separately, and the second layer of polysilicon is used as the gate. The thickness of the oxide layer between the two layers of polysilicon needs to be strictly controlled, otherwise leakage or lower breakdown voltage will result. The current method is to deposit a high-density plasma oxide layer (HDP silicon oxide) after the first layer of polysilicon is etched back, and then etch back, leaving an oxide layer of about 1500 Angstroms on the first layer of polysilicon. [0003] A specific manufacturing process of a tre...

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Problems solved by technology

[0013] In the above preparation method, since the HDP oxide layer is used as the dielectric layer between the two layers of polysilicon, the thickness of the dielectric layer between the two layers of polysilicon in the MOS device prepared by the above method is not uniform due to the limitation of the etching process, thus reducing the Electrical properties of the device

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