Formation method of vdmos device

Abstract

The present invention provides a method for forming a VDMOS device, comprising: providing a semiconductor substrate on which an epitaxial layer is formed; forming a sacrificial layer with an opening on the surface of the epitaxial layer, and the opening exposes the surface of the epitaxial layer; Oxidizing the epitaxial layer within the opening to form a first gate oxide layer; removing the sacrificial layer; thermally oxidizing the epitaxial layer to form a second oxide layer; depositing a polysilicon layer covering the first gate oxide layer layer and the second oxide layer; etching the polysilicon layer and the second oxide layer to form a gate structure; forming a source region, a source metal layer, a drain metal layer and a gate metal layer. The invention reduces the process difficulty of forming the gate oxide layer, increases the thickness of the gate oxide layer between the drain and the gate, reduces the capacitance value between the gate and the drain, and improves the switching speed of the VDMOS.

Description

technical field [0001] The invention relates to a power device, in particular to a method for forming a VDMOS device. Background technique [0002] Vertical double diffused metal oxide semiconductor field effect transistor (VDMOS), as a kind of power device, is widely used because of its advantages of high input impedance and low conduction voltage drop. The formation method of the prior art VDMOS device is as disclosed in the Chinese patent application whose publication number is CN 101515547A, specifically as figure 1 Shown is a schematic structural view of VDMOS, including: a semiconductor substrate 01, the semiconductor substrate 01 includes a semiconductor substrate 01a and an epitaxial layer 01b located on the semiconductor substrate 01a; a gate structure located on the surface of the epitaxial layer 01b, the The gate structure includes a gate oxide layer 02, a gate polysilicon layer 03 and a gate metal layer 07 sequentially located on the surface of the gate oxide la...

AI Technical Summary

Problems solved by technology

Because the first gate oxide layer 50 is located in the recessed opening, it is not easy to perform chemical mechanical polishing

[0014] Further, if the thickness of the first gate oxide layer 50 is small, it may be lower than the isolation structure between VDMOS devices, and the grinding process will cause damage to the isolation structure, affecting the isolation effect

[0015] Further, when ion implantation is performed on the epitaxial layer through the second gate oxide layer, the insulation performance of the second gate oxide layer will be damaged, thereby reducing the electrical performance of the VDMOS

[0016] At the same time, the above-mentioned gate polysilicon layer is divided into two parts, which increases the complexity of the formation process.

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