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Semiconductor structure and formation method, pmos transistor and formation method

A semiconductor and silicon-on-insulator technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of poor substrate, complex process flow, influence, etc., and achieve the effect of increasing volume and enhancing compressive stress

Active Publication Date: 2017-02-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such a method not only makes the entire process more complicated, but also the ion implantation process will have a negative impact on the substrate.

Method used

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  • Semiconductor structure and formation method, pmos transistor and formation method
  • Semiconductor structure and formation method, pmos transistor and formation method
  • Semiconductor structure and formation method, pmos transistor and formation method

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Comparison scheme
Effect test

Embodiment 1

[0040] Figure 2 to Figure 5 It is a schematic diagram of an embodiment of forming a semiconductor structure in the present invention.

[0041] First, if figure 2 As shown, a silicon-on-insulator substrate is provided, and the silicon-on-insulator substrate includes a silicon base 11 , an insulating buried layer 12 and a top layer of silicon 13 in sequence.

[0042] Optionally, the material of the buried insulating layer 12 is silicon oxide.

[0043] Such as image 3 As shown, the top silicon layer 13 is etched to expose the buried insulating layer 12 , and an active region is formed on the buried insulating layer 12 . The specific process is as follows: first coat a layer of photoresist layer (not shown) on the top layer of silicon 103, and define the pattern of the active region after the photolithography process; then use the photoresist layer as a mask, The top layer silicon 13 is etched in the active area pattern to expose the insulating buried layer 12 , and the act...

Embodiment 2

[0057] refer to Figure 7 to Figure 8 What is shown is a schematic diagram of a formation process of a PMOS transistor according to the present invention.

[0058] like Figure 7 As shown, a silicon-on-insulator substrate is provided, wherein the top-layer silicon 13a of the active region in the silicon-on-insulator substrate is bent upwards, and the specific method of forming the top-layer silicon 13a of the active region bent upwards is the same as that described in Embodiment 1. , which will not be repeated here.

[0059] continue to refer Figure 7 A gate dielectric layer 15 and a polysilicon gate 16 are sequentially formed on the top layer of silicon 13a in the active region; lightly doped regions 14 are formed in the top layer of silicon 13a in the active region on both sides of the polysilicon gate 16 . The specific formation process is as follows: a first photoresist layer (not shown) is coated on the top layer of silicon 13a in the active region; after exposure and...

Embodiment 3

[0065] Figure 9 to Figure 18 It is a schematic diagram of an embodiment process of forming a CMOS device structure of the present invention.

[0066] First, if Figure 9 As shown, a silicon-on-insulator substrate is provided, wherein the silicon-on-insulator substrate includes a silicon base 11 , an insulating buried layer 12 and a top layer of silicon 13 in sequence. Optionally, the material of the buried insulating layer 12 is silicon oxide or silicon nitride.

[0067] like Figure 10 As shown, the top layer silicon 13 is etched to expose the insulating buried layer 12, and the active region top layer silicon 13a of the PMOS device region and the active region top layer silicon 13b of the NMOS device region are formed on the insulating buried layer 12. The specific process is as follows: first coat a layer of photoresist layer (not shown) on the top layer of silicon 103, and after the photolithography process, respectively define the active area patterns of the PMOS devi...

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Abstract

The invention relates to a semiconductor structure and a forming method thereof, a PMOS (P-channel Metal Oxide Semiconductor) transistor and a forming method thereof. The forming method of the semiconductor structure comprises the following steps of: providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate sequentially comprises a silicon base, an insulated buried layer and top layer silicon; etching the top layer silicon until the insulated buried layer is exposed to form an active region; forming insulated oxide layers on the side wall and the top of the top layer silicon in the active region; and performing thermal oxidization treatment to ensure that the top layer silicon is bent upwards. The invention further provides a semiconductor structure, a PMOS transistor structure formed on the semiconductor structure and a forming method of the PMOS transistor structure. The invention aims to perform thermal oxidization treatment on the top layer silicon in a PMOS transistor device region so that the edge of the top layer silicon is bent upwards, so that the compression stress of the top layer silicon is enhanced and the performance of a subsequently-manufactured PMOS device is enhanced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method, a PMOS transistor and a forming method. Background technique [0002] With the continuous reduction of the size of CMOS devices, the short channel effect and carrier migration degradation effect of CMOS transistors are becoming more and more prominent. With the improvement of the performance requirements of semiconductor devices, the demand for the ability to suppress the short channel effect of the device and the ability to improve the carrier mobility is also becoming more and more prominent. [0003] In order to suppress the short channel effect of the device, the usual method is to increase the doping concentration of the substrate, increase the source / drain lightly doped region (LDD region), or use a thicker silicon-on-insulator (SOI) structure. Thin silicon substrate structure. However, increasing the dop...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L29/06H01L29/78H01L21/336
Inventor 李乐
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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