Single-chip asynchronous communication interface

Abstract

The invention discloses a single-chip asynchronous communication interface which comprises a clock module, an input and output controller and a synchronizing block, wherein the clock module is used for providing clock signals; the input and output module is used for asynchronous handshake communication with external network and generating a control signal to control data input and the output of the processed data; simultaneously the input and output module controls the startup and shutdown of the clock module; and the synchronizing block is used for dispensing, processing and synchronizing the input data stream according to the control signal of the input and output controller, and subsequently outputs the processed data to the external network. Under the driving of the clock by the synchronizing block, the single-chip asynchronous communication interface synchronizes and processes the input external network data according to the control signal of the input and output controller, and outputs the processed data to the external network, thus meeting the data synchronization and transmission among the asynchronous communication networks and further realizing the interconnection of different IP (internet protocol) cores in the networks.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a single-chip asynchronous communication interface. Background technique [0002] With the continuous advancement of integrated circuit process technology, under the deep submicron process node, integrated circuit design methodology has entered the System On A Chip (SOC, System On A Chip, System On A Chip) based on IP (Intellectual Property core, kernel module) core multiplexing technology. level chip) chip design. [0003] In SOC design, the interconnection structure between IP cores is the key to realizing IP core reusability and system scalability, and also the key to accelerating complex and large-scale SOC design and testing. As shown in Figure 1, the use of dedicated direct wires to achieve inter-core communication results in a large number of interconnect pins, long routing times, large routing areas, and non-scalable systems. Few designs use this approach; currently mo...

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Problems solved by technology

Because the clock frequency is affected by the maximum delay operation, it is not conducive to improving the operating frequency of the chip; the distribution of the system clock is becoming more and more complicated, which is not conducive to the realization of synchronous design and multi-clock design; when the internal operating frequency of the chip reaches GHz or higher, the clock drift The impact of clock distribution and interconnection delays cannot be ignored; for low power consumption, energy management for ineffective clock operations is also necessary

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