9 results about "Input output controller" patented technology

An integrated circuit (IC) chip and / or system includes a processing core and an input / output (I / O) controller, coupled to a host interface, to detect a plurality of state transitions in a data signal received over a system management bus (SMBUS) of the host interface and generate an interrupt responsive to detecting each state transition. An interrupt controller routes each interrupt to the processing core. The processing core, in response to receipt of each respective interrupt, retrieves a corresponding state transition received over the SMBUS and stores, in a memory, the corresponding state transition.

The invention provides a method, equipment and a program product for performing input / output access control by a Linux kernel. The method comprises the steps that an input and output access request initiated by an application program through an upper layer driving interface of the Linux kernel is obtained, and the input and output access request carries a read-write port address; intercepting the input and output access request, and determining a target input and output controller corresponding to the read-write port address according to registration information of registered input and output controllers; and calling a driving program of the target input and output controller to execute a read-write operation corresponding to the input and output access request. The method and device are used for solving the problem that in the prior art, in order to adapt to different instruction set architectures, Linux kernel upper layer drive framework codes need to be modified.

Provided is a nonvolatile memory including a plurality of planes including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; an input / output controller configured to receive commands and addresses, input / output data, and set each plane to a ready status or a busy status; a control logic circuit configured to control the plurality of planes based on commands, and detect a fixed-time read command; and a status delay logic configured to determine a target plane and a bit level based on an address received with the fixed-time read command, and determine a delay time based on the bit level, and the input / output controller is configured to change the target plane from the ready status to the busy status, and restore the target plane from the busy status to the ready status.

The invention provides a boron neutron capture therapy target control system based on an EPICS architecture. The boron neutron capture therapy target control system comprises an equipment control level, an input and output controller IOC and an operator interface OPI which are connected in sequence. The equipment control level is used for monitoring and controlling physical equipment of the target system through a programmable logic controller (PLC); the input and output controller IOC is used for running a distributed real-time database and an equipment driving program so as to perform data exchange and communication between the equipment control level and the operator interface OPI; and the operator interface OPI is used for providing a graphical interface so as to display real-time data, state and alarm information of the system, and receiving an operation instruction. The purposes of high integration level and good real-time performance are achieved.

Apparatus and method for a reconfigurable processor for prefill and decode operations. An example processor comprises: compute circuitry to perform compute operations associated with prefill phase of an LLM workload in which first tokens of an input prompt are processed in parallel and a decode phase in which response tokens are generated sequentially; a memory controller; an input / output (I / O) controller; an interconnect fabric; and a management controller to select between a first plurality of operational modes responsive to detecting the prefill phase and a second plurality of operational modes responsive to detecting the decode phase, wherein the first plurality of operational modes are selected to enhance performance of the compute circuitry and the second plurality of operational modes are selected to enhance performance of the memory controller and the interconnect fabric.

The utility model relates to input / output controller technical field discloses an input / output controller based on thyristor, including multiple thyristor module, and the thyristor module includes triode switch Q1, input / output protection module, gate pulse trigger module and gate protection module, input / output protection module connects to triode switch Q1's base and collector respectively, gate pulse trigger module connects to triode Q1's emitter and collector respectively, and gate protection module is connected to gate pulse module, and each thyristor module is mutually connected in series and forms controller switch, and the controller switch is formed by the series connection setting multiple thyristor modules, need not to set up peripheral heating circuit, makes the controller switch to have extremely low heat loss, can use stably under the vibration and rotation environment, and lower cost.

The application relates to the technical field of automatic control, and provides a parameter calibration method, device, equipment and medium based on EPICS. The method is characterized in that: each device in a controlled system is electrically connected with an input / output controller of an EPICS system, a database template file is configured based on an electrical connection relationship, a function module of each device in the controlled system is predefined, when a target parameter calibration instruction is received, the target parameter calibration instruction is parsed to obtain N instruction segments in sequence, after instruction recognition, a function module corresponding to each instruction segment is acquired, and an execution parameter in the target parameter calibration instruction is input into the function module, so that parameter calibration is completed by sequentially executing the function modules corresponding to the N instruction segments, an automatic control process of parameter calibration is realized, the parameter calibration no longer completely depends on a fixed program written in underlying code, programming does not need to be adjusted every time the experimental process is stopped, the calibration complexity is reduced, and the calibration efficiency is improved.

The invention relates to a data writing method and device, an input and output controller and a processor chip. The method comprises the following steps: receiving a first write request, and caching a first request message of the first write request; sending the first write request to a consistency master node to indicate the consistency master node to perform consistency maintenance on the first write request; receiving a second write request, and caching a second request message of the second write request; under the condition that the first access address is the same as the second access address, merging the first data and the second data to obtain target write-in data; and under the condition that a consistency maintenance completion message of the first write request returned by the consistency master node is received, sending target write data to the consistency master node so as to indicate the consistency master node to execute a data write operation corresponding to the target write data. By adopting the method, the problems of time delay and bandwidth caused by traditional data serial writing can be eliminated, and the effects of improving the data transmission efficiency and simplifying the data transmission process are achieved.

Provided are a nonvolatile memory and a storage device, the nonvolatile memory including: a plurality of planes including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; an input / output controller configured to receive a command and an address, input / output data, and set each plane to a ready state or a busy state; a control logic circuit configured to control the plurality of planes based on the command and detect a fixed time read command; and a state delay logic configured to determine a target plane and a bit level based on an address received with the fixed time read command and determine a delay time based on the bit level, and the input / output controller is further configured to change the target plane from the ready state to the busy state and restore the target plane from the busy state to the ready state.