Method for manufacturing resistive type memory

Abstract

The invention provides a method for manufacturing a resistive type memory, comprising the following steps: constructing a picture for a lower electrode and carrying out oxygen ion implantation on the lower electrode to form an oxide storage medium layer on the lower electrode; annealing the oxide storage medium layer; and constructing a picture on the oxide storage medium layer and forming an upper electrode. By using the method, an empty hole is not generated between the storage medium layer and the lower electrode; and the oxygen storage medium layer is even, and O elements are distributed evenly in the oxygen storage medium layer. The resistive type memory manufactured by the method has the advantages of low manufacturing cost and good effect and is easy to integrate with a CMOS (complementary metal oxide semiconductor) technology.

Description

technical field [0001] The invention relates to a preparation method of a semiconductor device, in particular to a preparation method of a resistive memory. Background technique [0002] Memory occupies an important position in the semiconductor market. Due to the continuous popularization of portable electronic devices, the share of non-volatile memory in the entire memory market is also increasing, and more than 90% of the share is occupied by flash memory (Flash Memory). However, due to the requirements for storing charges, the floating gate of flash memory cannot be thinned without limit with the development of technology. It is reported that the limit of flash memory technology is around 32nm, which forces people to look for the next generation of non-volatile gates with better performance. memory. [0003] Recently, resistive switching memory (Resistive Switching Memory) has attracted high attention due to its characteristics of high density, low cost, and the abilit...

AI Technical Summary

Problems solved by technology

Cu prepared by this method x O-based resistive memory is cheap and easy to integrate with CMOS process, but it has the following disadvantages: (1) It is easy to integrate on Cu x Voids between O storage medium and Cu matrix

(2) Since the Cu interconnection is generally a polycrystalline structure, when it is oxidized by plasma oxidation or thermal oxidation, the oxidation rate of the grain and the grain boundary is different, resulting in the formation of Cu x O film uniformity is poor

(3) Cu x The distribution of O element in the O film is directly related to the performance of the device. It is difficult to effectively control the distribution of O element in the film by plasma oxidation or thermal oxidation.

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