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Semiconductor device

A semiconductor and nitride semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve the problems of increased occupation area, increased cost, increased number of peripheral components, etc., and achieves the effect of high switching performance

Inactive Publication Date: 2012-01-11
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since external resistors are required for the gate, the number of peripheral components increases, the occupied area increases, and the cost increases.

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0048] A first embodiment will be described with reference to the drawings. figure 1 A cross-sectional structure of the semiconductor device according to the first embodiment is shown. Such as figure 1 As shown, the semiconductor device of this embodiment is an HFET formed on a substrate 101 . The substrate 101 may be Si, sapphire, silicon carbide (SiC), GaN, or the like. A buffer layer 103 having a film thickness of 2 μm is formed on the substrate 101 . On the buffer layer 103 is formed a semiconductor layer stack 105 including a first nitride semiconductor layer 106 made of undoped GaN with a thickness of 3 μm and an undoped AlGaN with a film thickness of 25 nm. The second nitride semiconductor layer 107 is sequentially stacked.

[0049] A first ohmic electrode 111 serving as a source electrode and a second ohmic electrode 113 serving as a drain electrode are formed on the semiconductor layer stack 105 . It is sufficient that the first ohmic electrode 111 and the second...

no. 2 approach

[0056] Hereinafter, a second embodiment will be described with reference to the drawings. Figure 5 The planar structure of the semiconductor device of 2nd Embodiment is shown. But when Figure 5 Only the arrangement of electrodes and pads is shown in , and the description of the insulating film covering the electrodes, the plugs connecting the electrodes and the pads, etc. is omitted. In addition, in Figure 5 in, right with figure 1 The same components are given the same symbols and their descriptions are omitted. Such as Figure 5 As shown, the semiconductor device of the second embodiment is a multi-finger type HFET. By forming it into a multi-finger type, efficient layout can be realized. Therefore, the gate width of the HFET can be made very large, and a power device capable of operating with a large current can be realized.

[0057] The semiconductor layer stack 105 is formed on the substrate with the buffer layer interposed therebetween. A first ohmic electrode...

no. 3 approach

[0066] Hereinafter, a third embodiment will be described with reference to the drawings. Figure 10 A planar structure of the semiconductor device of the third embodiment is shown. But when Figure 10 Only the arrangement of the electrodes and pads is shown in , and the description of the insulating film covering the electrodes, the plugs connecting the electrodes and the pads, etc. is omitted. In addition, in Figure 10 in, right with Figure 5 The same symbols are assigned to the same constituent elements, and their descriptions are omitted.

[0067] In the semiconductor device of the present embodiment, a diode 241 is formed instead of the resistance element 231 . Such as Figure 11 As shown, a diode 241 has a p-type AlGaN layer 243 and a cathode electrode 245 . The p-type AlGaN layer 243 is formed on a portion of the semiconductor layer stack 105 that has not been made highly resistive. Therefore, a 2DEG layer is formed at the heterojunction interface below the p-ty...

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PUM

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Abstract

A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly, to nitride semiconductor devices usable as power transistors and the like. Background technique [0002] Nitride semiconductors represented by gallium nitride (GaN) are wide bandgap semiconductors, and in the case of GaN and AlN, for example, the bandgaps at room temperature are as large as 3.4 eV and 6.2 eV, respectively. Nitride semiconductors have characteristics such as a large dielectric breakdown electric field and a higher saturation drift velocity of electrons than compound semiconductors such as gallium arsenide (GaAs) or silicon (Si) semiconductors. In addition, in the heterostructure of AlGaN and GaN, charges are generated at the heterointerface by spontaneous polarization and piezoelectric polarization on the (0001) plane. The surface carrier concentration of charges generated at the heterointerface is 1 × 10 even without doping 13 cm -2 above. By using the t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/338H01L21/337H01L21/822H01L21/8232H01L27/04H01L27/06H01L27/095H01L29/778H01L29/80H01L29/808H01L29/812
CPCH01L29/7787H01L29/7783H01L29/42316H01L27/0605H01L29/1066H01L29/2003H01L29/86
Inventor 柴田大辅森田竜夫柳原学上本康裕
Owner PANASONIC CORP