Pattern matching based FPGA (field-programmable gate array) logic synthesis method

A logic synthesis and matching technology, applied in the field of FPGA logic synthesis, can solve the problems of not being able to obtain the optimal solution, unable to generate the optimal equivalent logic netlist, etc., and achieve low power consumption, small logic resource occupation, and small clock delay Effect

Inactive Publication Date: 2012-03-14
AGATE LOGIC BEIJING
View PDF3 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] For the FPGA chip architecture containing improved logic units, if the existing logic synthesis method is used for logic synthesis, the optimal solution cannot be obtained, that is, the optimal equivalent logic netlist represented by the original FPGA logic resources cannot be generated

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Pattern matching based FPGA (field-programmable gate array) logic synthesis method
  • Pattern matching based FPGA (field-programmable gate array) logic synthesis method
  • Pattern matching based FPGA (field-programmable gate array) logic synthesis method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] Figure 5 It is a logic synthesis flowchart of an embodiment of the present invention.

[0035] In step 510, this step is an RTL level circuit design phase. In this stage, users describe the functions they want to achieve through hardware description languages ​​(Verilog, VHDL, etc.).

[0036] In step 520, syntax scanning is performed on the RTL level circuit in step 510, and a syntax tree ParserTree is generated after syntax scanning, and then the establishment and refinement process Elaboration is generated to generate an internal data structure EDB (Elaborated Database).

[0037] The syntax scanning can adopt any conventional syntax scanning method, such as using a scanning program generated by open source software tools such as Flex, Flex++, Flexc++, etc. to perform syntax scanning to generate a syntax tree and an internal data structure EDB.

[0038] In step 530, traverse the syntax tree obtained in step 520, and execute a pattern matching comprehensive algorithm...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a pattern matching based FPGA (field-programmable gate array) logic synthesis method, which comprises the following steps of: firstly, generating data structures of modules to be matched according to an RTL (resistor transistor logic) level circuit set by a user; then, loading a predefined sequence module and a predefined combination module for explanation; selecting eachmodule to be matched and corresponding data structure thereof in the RTL level circuit one by one, and judging whether the selected module to be matched is matched with each predefined module; and once the module to be matched is matched with one of the predefined modules, instantiating the predefined module. By using the logic synthesis method provided by the invention, the occupancy amount of on-chip logic resources is smaller, and the time delay for logic implementation is smaller, therefore, the method can be widely used in FPGA logic synthesis.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to an FPGA logic synthesis method. Background technique [0002] In the IC design process, logic synthesis is a very important link in the back-end design. Logic synthesis is the process of converting the RTL-level (Register Transfer Level) circuit described by the hardware description language into a circuit structure model (circuit netlist) according to the basic circuit unit library provided by the chip manufacturer. [0003] The existing logic synthesis process starts from the original circuit diagram, and after logical analysis, a detailed description of the circuit is obtained, and then logical optimization is performed to obtain a simplified logical expression, and the mapping relationship with the actual circuit unit is obtained through logical mapping. Finally, based on this The mapping relationship gives the circuit analysis. [0004] FPGA (Field Programmable Gate Array, Field Pr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 樊平王海力
Owner AGATE LOGIC BEIJING
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap