Method for manufacturing polycrystalline gate structure

Abstract

The invention provides a method for manufacturing a polycrystalline silicon gate structure. The method comprises the following steps of: providing a front-end device structure, wherein a polycrystalline silicon layer is formed on the front-end device structure and impurities are predoped in the part from the surface to the preset depth of the polycrystalline silicon layer; forming a masking layer on the surface of the polycrystalline silicon layer, and forming a photoinduced resist layer with patterns on the masking layer; taking the photoinduced resist layer as a mask and carrying out first etching on the masking layer and the polycrystalline silicon layer, wherein the etching depth of the polycrystalline silicon layer is larger than the preset depth and is less than the thickness of the polycrystalline silicon layer; removing the photoinduced resist layer; forming side-wall oxidizing layers on the side wall of the masking layer and the side wall of the polycrystalline silicon layer; and taking the masking layer and the side-wall oxidizing layers as masks, and carrying out second etching on the polycrystalline silicon layer till the surface of the front-end device structure is exposed. According to the method, a polycrystalline silicon gate structure with accurate line width and better LER (line edge roughness) can be formed, so that the electric performance of a semiconductor device is improved.

Description

Technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a polysilicon gate structure. Background technique [0002] At present, driven by the demand for miniaturization, high-density, high-speed, high-reliability, and system integration of semiconductor devices, the minimum feature size of semiconductor devices has entered the era of 45nm and below nodes. The composition and structure of the semiconductor device simply scaled down will become infeasible due to excessive leakage. Therefore, while the semiconductor device is scaled down, the leakage will be reduced by changing part of the composition or structure. [0003] As early as when the minimum feature size of semiconductor devices entered the 90nm node era, polysilicon materials were widely used in the production of complementary metal oxide semiconductor field effect transistors (CMOSFETs, due to their better heat resistance a...

AI Technical Summary

Problems solved by technology

Specifically, as Figure 1D As shown in , the polysilicon line in the polysilicon gate structure in the second region 100N obviously "necked" (necking) , resulting in narrowing of the channel, thereby causing the short channel effect

In addition, severe "necking" may also cause disconnection of polysilicon lines

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