All-digital clock data recovery device and transceiver implemented thereof

Abstract

The present invention relates to a clock data recovery apparatus having all circuits thereof digital-circuitized through a digital filter and a digitally controlled oscillator (DCO). A DCO according to the present invention has a chain of plural inverters, and a variable resistance switch matrix is configured between the inverters and a voltage source for supplying a source current to each of the inverters to tune the oscillation frequency through variation of a supply voltage. Here, the variable resistance switch matrix is implemented by using a PMOS transistor array, and meanwhile a vertical resistance is further inserted between columns of the switch matrix to equalize between the frequency tuning step at a lower level and the frequency tuning step at a high level. Also, to resolve the occurrence of jitter problems, a primary sigma delta modulator is used for implementing a dithering circuit and a segment thermometer scheme is applied to tune a DCO with a smaller number of routing lines.

Description

technical field [0001] The present invention relates to a clock data recovery (clock data recovery; CDR) and its related transceiver (transceiver), especially a clock data recovery device, which recovers a clock signal and data from a data bit stream (bit stream) input in a serial data communication mode There are no analog circuits in all the circuits, only digital circuits. Background technique [0002] Recently, gigabit per second (GB / s) high-speed serial interface (serial link) communication methods have become popular, and serial interface transceivers are installed in a single chip. These serial interface chip-to-chip (chip-to-chip) chip) communication, in order to prevent the receiving side from transmitting a clock signal separately, only data is transmitted through the communication channel. Therefore, clock data recovery (CDR) for retrieving clock information and data information from the serial data bits is required in order to process gigabits per second serial ...

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Problems solved by technology

[0014] Therefore, it will be difficult to form an analog circuit mode charge excitation circuit in an integrated circuit project with a power supply voltage below 1.0V.

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