Method for enhancing n channel electronic activity

Abstract

The invention provides a method for enhancing n channel electronic activity. The method comprises the following steps that: an offset spacer is formed around a polysilicon gate above a substrate that is at the position of an n channel; a main spacer is formed; source and drain implantation is carried out; the main spacer is removed; a tension force layer is deposed on the surface layer of the substrate; the tension force layer on the surface layer of the substrate is removed; amorphization processing is carried out on the surface layer of the substrate; and nickle silicide is respectively formed on the top, the source electrode and the drain electrode of the polysilicon gate. According to the invention, a tension force layer is directly applied on a polysilicon gate, wherein a protection layer of a main spacer of the polysilicon gate has been removed; therefore, a technical bottleneck of a tensile stress of a n channel in the prior art can be solved, so that activities of electrons in the n channel can be effectively enhanced.

Description

technical field [0001] The invention relates to a processing method of an nMO SFET (n metallic oxide semiconductor field effect transistor, n channel metal oxide semiconductor field effect transistor), in particular to a method for enhancing n channel electronic activity in the nMOSFET. Background technique [0002] At present, with the continuous improvement of processing technology, the processing of integrated circuits has entered the era of 65 / 45 nanometer (nm) technology, and nickel silicide (NiSi) is becoming the material of choice for contact applications. nMOSFETs use electrons as the majority carriers, so the channel is n-type. As the size of MOSFETs continues to decrease, some people use the following methods to increase the electron mobility of the n-channel, such as Figure 1-5 As shown: a compensation spacer 102 (offset spacer) protection layer is formed around the polysilicon gate 101, such as figure 1 As shown; the main spacer 105 (main spacer) is formed on ...

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Problems solved by technology

[0003] However, the method of the above-mentioned technical solution is limited to the improvement of the electron mobility in the n-channel. Specifically, due to the existence of the main sidewall 105 protective layer around the formed polysilicon gate, the silicon nitride layer cannot directly conduct the polysilicon gate. effect, the protective layer of the main sidewall 105 bears a large part of the tensile stress from the silicon nitride layer 106, resulting in limited tensile stress for the formation of the n-channel

In addition, even if the tension of the silicon nitride layer can continue to be increased, cracks are more likely to appear at the edge of the polysilicon gate as the tension increases. If cracks occur, it will seriously affect the quality of nMOSFET products

That is to say, a large part of the limited tensile stress provided by the silicon nitride layer 106 is taken up by the protective layer of the main sidewall 105, which leads to a bottleneck in the improvement of electron mobility in the n-channel.

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