A method for preparing a bottom gate self-aligned zinc oxide thin film transistor

Abstract

The invention discloses a method for preparing a bottom gate self alignment zino oxide film transistor. The preparation method employs a bottom gate structure; a non-transparent conductive film is grown and photoetching and etching are carried out to form a gate electrode; a gate medium layer and an active region layer are grown continuously; photoetching and etching are carried out to form an active region; and by using the gate electrode as a mask layer as well as enabling masks of a source electrode and a drain electrode to be cooperated with, back exposure is carried out, so that self alignment is realized. Because self alignment of the source electrode, the drain electrode and the gate electrode is realized, parasitic capacitance of the gate electrode and the source electrode and the drain electrode is substantially reduced, so that driving capability of the circuit of the film transistor can be improved. The improvement of the preparation method is that lights pass through the masks of the source electrode and the drain electrode when back exposure is carried out as well as after the photoetching, a peeling technology is combined so as to form regions of the source electrode and the drain electrode once. The whole process only needs three steps of photoetching, so that one step of photoetching processing is saved. And because the photoetching cost is a sensitive problem according to the microelectronic technology, the preparation method enables the process flow to be simplified and manufacturing cost to be saved.

Description

technical field [0001] The invention belongs to the field of flat panel display, and in particular relates to a method for preparing a bottom gate self-aligned zinc oxide thin film transistor. Background technique [0002] At present, flat panel display technology is developing rapidly, and it is extremely important to promote the development of flat panel display to improve the performance of the thin film transistor as a pixel driving unit and reduce its manufacturing cost. Although the bottom-gate non-self-aligned device of the traditional hydrogenated amorphous silicon thin film transistor TFT has low manufacturing cost, its low performance has become a bottleneck restricting the continuous improvement of flat panel display technology. In view of this, both academia and industry are actively developing new TFT materials and new device structures. However, it is impossible to meet the multiple requirements of fast speed, large size, uniform high quality, and organic ligh...

AI Technical Summary

Problems solved by technology

[0004] In terms of devices, when a higher frame rate is required to improve the display quality, or when the 3D mode is used for display, the display frequency and driving current need to be increased. The non-self-aligned bottom gate structure widely used now has a large gate drain Over-coverage capacitors are increasingly unable to meet the requirements of high-performance displays, which limits the development of the entire flat-panel display industry

[0005] However, compared with traditional amorphous silicon thin film transistors, the manufacturing cost of zinc oxide thin film transistors is greatly increased, which hinders the popularization of zinc oxide thin film transistors.

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