Mixed bonding structure for three-dimension integration and bonding method for mixed bonding structure

Abstract

The invention relates to a mixed bonding structure for three-dimension integration and a bonding method for the mixed bonding structure. The mixed bonding structure for the three-dimension integration comprises a first substrate. The first substrate is provided with bonding interconnection metal electrically connected with the first substrate; the other end part of the bonding interconnection metal, which is correspondingly connected with the first substrate, is sunk to form a cavity; a first dielectric adhesion layer covers at the periphery of the bonding interconnection metal on the first substrate; the bonding interconnection metal is encircled by the first dielectric adhesion layer; and the first dielectric adhesion layer is lower than the edge of the bonding interconnection metal. According to the mixed bonding structure for the three-dimension integration, the first dielectric adhesion layer is lower than the edge of the top part of a salient point, and when bonding is performed under the pressure action, the edge of the top part of the salient point is bonded with a pad of a second substrate, and thereby, the dielectric adhesion layer can be stopped entering the surface of the bonding interconnection metal, which is bonded with the pad, and the open circuit problem and the reliability problem can be avoided. The mixed bonding structure for the three-dimension integration is compact in structure and is convenient in process operation.

Description

technical field [0001] The invention relates to a hybrid bonding structure and a bonding method thereof, in particular to a hybrid bonding structure for three-dimensional integration and a bonding method thereof, belonging to the technical field of integrated circuits. Background technique [0002] The core technologies of 3D integrated circuits include TSV (Through Silicon Via) fabrication, wafer thinning, thin wafer handling, and bonding technologies. These technologies are all extremely challenging. The bonding technology includes chip-to-chip, chip-to-wafer and wafer-to-wafer bonding. For the above three bonding technologies, there are two materials for electrical interconnection, one is metal bumps, such as Cu, Au, etc.; the other is solder bump interconnection, such as Sn, In, etc. [0003] The advantage of using metal bump interconnection in three-dimensional integrated circuits is that a small interconnection pitch can be obtained, and Cu-Cu bump bonding can obtain...

AI Technical Summary

Problems solved by technology

[0003] The advantage of using metal bump interconnection in three-dimensional integrated circuits is that a small interconnection pitch can be obtained, and Cu-Cu bump bonding can obtain excellent electrical performance and reliability; the disadvantage is that the metal bumps are required to have a high Flatness, usually requires high bonding temperature (>300°C), and special surface treatment to remove oxides on the metal surface

Further, due to the increase in interconnection density, the pressure required for bonding is increasing, which will cause damage to 3D integration, especially thin chips with TSV structures

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