Side wall cavity layer structure of semiconductor device and method for preparing side wall cavity layer structure

Abstract

The invention provides a side wall cavity layer structure of a semiconductor device, which comprises a semiconductor substrate, a grid electrode, a dielectric layer and a contact hole. Cavity layers are disposed on two sides of the grid electrode, and SiO2 layers are disposed between each cavity layer and the grid electrode and between each cavity layer and the semiconductor substrate. The invention further provides a method for preparing the side wall cavity layer structure of the semiconductor device. The method includes steps: depositing an amorphous carbon layer on the semiconductor substrate with the grid electrode and forming amorphous carbon side walls by means of self-alignment etching; chemically and mechanically grinding the dielectric layer until the amorphous carbon side walls are exposed, then carrying out ashing treatment to completely ash and clean the amorphous carbon side walls, and continuing ashing until a SiO2 layer is formed on the grid electrode and an exposed silicon surface; and quickly filling the dielectric layer so that holes are kept on portions without the amorphous carbon side walls. The side wall cavity layer structure of the semiconductor device is simple, and the method is simple, convenient and feasible.

Description

technical field [0001] The invention belongs to the field of semiconductor technology, and relates to a semiconductor device sidewall structure and a preparation method thereof, in particular to a semiconductor device sidewall cavity layer structure and a preparation method thereof. Background technique [0002] Short Channel Effect (Short Channel Effect) is a common phenomenon when the channel length of CMOS devices is reduced. Press down) and other characteristics, in severe cases, it will cause the performance of CMOS devices to fail. [0003] The principle can be explained by the charge sharing model, that is, when the channel becomes shorter, the ratio of the charge in the channel depletion region shared by the source liner and the drain liner PN junction to the total charge in the channel will increase, resulting in a decrease in gate control capability. [0004] However, the traditional charge sharing model does not take into account the effect of the fringe electric...

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Problems solved by technology

At the same time, as the size of the device continues to decrease, the thickness of the sidewall also decreases. At this time, the effect of the contact hole on the gate potential through the capacitive coupling of the sidewall will become larger.

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