Method for producing two layers of semiconductor devices with half empty structure

Abstract

According to the invention, the methods of low-temperature bonding and low-temperature exfoliation are utilized to achieve the layer transfer of an upper semiconductor layer above a lower semiconductor device layer, then an upper semiconductor device is produced in the upper semiconductor layer, and finally, the processes for an upper contact hole and a lower contact hole are completed in one time to realize isolation in production of the upper and the lower layers of semiconductor devices. The method provided by the invention has the advantage of simple process. The integration level of the semiconductor devices is increased effectively. Additionally, a half empty isolation structure of an empty layer and the lower contact hole is produced between the upper and the lower layers of the semiconductor devices to effectively reduce the capacitance coupling effect between the upper and the lower layers of the semiconductor devices.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor device, in particular to a method for preparing an upper and lower layer semiconductor device with a half-hole isolation structure. Background technique [0002] Due to its unique structure and a series of excellent properties, SOI (Silicon On Insulator) can realize the insulation isolation of components in integrated circuit manufacturing and eliminate the parasitic latch effect in bulk silicon CMOS; at the same time, CMOS / SOI circuits also have parasitic capacitance A series of advantages such as small size, high integration, fast speed, low power consumption, high working temperature (300°C), and radiation resistance. Therefore, SOI materials will be one of the main materials for thinner line (0.1μm) integrated circuits. It is expected that the above materials will be mainly used when the integration level reaches 1Gb and uses Φ300mm silicon wafers. In recent years, the rapid developme...

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Problems solved by technology

[0005] Chinese patent CN1610114A discloses a three-dimensional complementary metal-oxide-semiconductor device (CMOS) structure and its preparation method. It adopts low-temperature bonding and low-temperature lift-off technology, which can realize multi-layer stacking of CMOS and increase device integration density, but has the following defects : A layer of metal layer needs to be added between layers, and the upper and lower layers of devices are connected to it through through holes; this increases the complexity of the process

[0006] Chinese patent CN100440513C discloses a three-dimensional complementary metal-oxide-semiconductor (CMOS) device structure and its preparation method. It adopts low-temperature bonding and low-temperature lift-off technology, which can realize multi-layer stacking of CMOS and increase the integration density of devices. Although it is in two There is no need to add a metal layer between the device layers as the connection layer between the upper and lower device layers, but it still needs to prepare connection through holes between the device layers of each layer as the connection line between the upper and lower device layers, which also increases the process complexity

[0007] Both of the above two patented technologies realize the multi-layer stacking of CMOS, and the multi-layer stacking will inevitably increase the parasitic capacitance between semiconductor devices, thus limiting the response speed of the circuit

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