Memory and method of forming the same
A memory and well region technology, which is applied in the manufacture of electric solid state devices, semiconductor devices, and semiconductor/solid state devices, etc., can solve the problems of high voltage coupling coefficient, low performance, and large energy consumption of programmable memory, and achieves improved performance and improved performance. The effect of increasing performance and quantity
Active Publication Date: 2016-08-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0008] However, the voltage coupling coefficient of the existing erasable and writable programmable memory is still relatively high, and a high operating voltage needs to be applied to the memory, so the energy consumption of the erasable and writable programmable memory is large and the performance is low. Low
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[0064] As described in the background art, please refer to figure 1 , when the existing multi-erasable programmable memory works, the second source / drain region 108 is grounded, and a bias voltage is applied to the first source / drain region 105; and when the first source / drain region 105 is loaded with a negative bias voltage When the first source / drain region 105 is loaded with a positive bias voltage, the memory performs an erase operation.
[0065] Specifically, when the memory performs programming or erasing operations, the second source / drain region 108 is grounded, and the first source / drain region 105 is loaded with a bias voltage V p , and when performing a program operation the bias voltage V p is less than 0, while performing an erase operation when the bias voltage V p greater than 0; then when the memory is in operation, a potential V will be generated on the gate connection layer 109 g .
[0066] The inventors of the present invention have found through resea...
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A memory and a method of forming the same, wherein the memory includes: a semiconductor substrate, a first well region located within the semiconductor substrate and a second well region isolated from the first well region; a first gate dielectric layer; a first gate electrode located on the surface of the first gate dielectric layer; a first source / drain region located on both sides of the first gate dielectric layer and the first gate electrode; a second gate located on the surface of the second well region dielectric layer; a second gate electrode located on the surface of the second gate dielectric layer; a second source / drain region located on both sides of the second gate dielectric layer and the second gate electrode; between the first gate electrode and the second gate electrode The gate connection layer electrically connects the first gate and the second gate, and the gate connection layer is electrically isolated from the surface of the semiconductor substrate through the first insulating layer; an interlayer dielectric layer located on the surface of the first gate; The metal layer on the surface of the interlayer dielectric layer; the first conductive plug located on the surface of the first well region electrically connects the metal layer to the first well region. The performance of the memory is improved.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a memory and a forming method thereof. Background technique [0002] Electrical multiple time programmable memory (multiple time program, MTP) is a relatively common non-volatile memory, and because of the simple manufacturing process and low cost of the electrical multiple time programmable memory, it has been widely used. Applications, for example, are set in embedded systems, PCs and peripherals, telecommunication switches, cellular phones, network interconnection and other equipment to store information such as voice, image or data. [0003] Please refer to Figure 1 to Figure 4 ,in figure 1 It is a schematic diagram of the top view structure of the existing multiple erasable programmable memory, figure 2 for figure 1 The cross-sectional structure diagram in the direction of AA', image 3 for figure 1 The cross-sectional structure diagram in the d...
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IPC IPC(8): H01L27/115H01L21/8247H10B69/00
Inventor 张博
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP