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Configurable network-on-chip fault tolerance method

An on-chip network, fault-tolerant mechanism technology, applied in the field of fault-tolerance, can solve the problems of high delay and high power consumption of fault-tolerant strategies, and achieve the effect of improving reliability

Inactive Publication Date: 2015-01-14
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a configurable on-chip network fault-tolerant method for the problems of high power consumption and high delay in the fault-tolerant strategy of existing soft errors

Method used

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  • Configurable network-on-chip fault tolerance method
  • Configurable network-on-chip fault tolerance method
  • Configurable network-on-chip fault tolerance method

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Experimental program
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specific Embodiment approach 1

[0023] Specific implementation mode one, the following combination Figure 1 to Figure 5 Describe this embodiment, the configurable network-on-chip fault-tolerant method described in this embodiment is implemented based on a router, and the router includes a CRC encoding module, a CRC decoding module and a fault-tolerant mechanism selection module. In the input channel, different reliability The data packet enters the virtual channel after being encoded by the CRC encoding module. In the output channel, the data packet output by the register is decoded by the CRC decoding module and then output. The fault tolerance mechanism selection module controls the selection of the crossbar according to the format of different reliability data packets in the input channel. the corresponding transport mechanism;

[0024] The configurable on-chip network fault tolerance method based on the above router is:

[0025] The source node sends different reliability data packets to the reliabilit...

specific Embodiment approach 2

[0035] Specific embodiment two: combine Image 6 Describe this implementation mode, this implementation mode is a further limitation of the configurable network-on-chip fault-tolerant method described in the specific embodiment one, A-level reliability fault-tolerant strategy, which includes the following steps:

[0036] Step 1: Redundant backups are set for the header flakes, data flakes and tail flakes of data packet A required for high reliability of α%;

[0037] Step 2: Carry out CRC encoding to the redundant backup described in step 1 into the original data packet;

[0038] Step 3: Set up a redundant backup for the original data packet, and use the End-and-Hop data transmission mechanism for data transmission;

[0039] Step 4: Select a routing algorithm to transmit the original data packet and redundant backup:

[0040] Use the XY routing algorithm to transmit the original data packet, and use the YX routing algorithm to transmit the redundant backup data packet;

[00...

specific Embodiment approach 3

[0045] Specific embodiment three: combine Figure 7 Describe this implementation mode, this implementation mode is a further limitation of the configurable network-on-chip fault-tolerant method described in the specific embodiment one, the B-level reliability fault-tolerant strategy, which includes the following steps:

[0046] Step 1: The medium reliability of β% requires the data chip of data packet B to be set as redundant backup;

[0047] Step 2: Carry out CRC encoding to the redundant backup described in step 1 into the original data packet;

[0048] Step 3: Set up a redundant backup for the original data packet, and use the Hop-by-Hop data transmission mechanism for data transmission;

[0049] Step 4: Select a routing algorithm to transmit the original data packet and redundant backup:

[0050] Use the XY routing algorithm to transmit the original data packet, and use the YX routing algorithm to transmit the redundant backup data packet;

[0051] Step five: set a pari...

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Abstract

The invention discloses a configurable network-on-chip fault tolerance method, relates to a fault tolerance method, and aims to solve the problems of high power consumption, high delay and the like of the conventional soft error fault tolerance strategy. According to the method, improvement is made aiming at a router structure, a transmission mechanism and a data packet format; alpha percent high reliability requirement data packet A selects an A level reliability fault tolerance strategy and an End-and-Hop data transmission mechanism to transmit data to a destination node; beta percent moderate reliability requirement data packet B selects a B level reliability fault tolerance strategy and a Hop-by-Hop data transmission mechanism to transmit data to the destination node; gamma percent low reliability requirement data packet C selects a C level reliability fault tolerance strategy and an End-to-End data transmission mechanism to transmit data to the destination node; delta percent no reliability requirement data packet D selects a D level reliability fault tolerance strategy and an End-to-End data transmission mechanism to transmit data to the destination node; and the sum of alpha percent, beta percent, gamma percent and delta percent is equal to one. The configurable network-on-chip fault tolerance method is used for fault tolerance aiming at soft error.

Description

technical field [0001] The invention relates to a fault-tolerant method, in particular to a configurable on-chip network fault-tolerant method. Background technique [0002] According to the forecast in ITRS (International Technology Roadmap for Semiconductors, International Technology Roadmap for Semiconductors), by 2018, the number of transistors integrated on a single chip will reach 256 billion. A single chip integrates more and more IP, and the traditional bus interconnection is replaced by NoC (Network on Chip) is the future development trend. However, as the size of the chip decreases, it is more susceptible to frequent soft errors caused by factors such as crosstalk, electromagnetic interference, and electromigration. The reliability and fault tolerance of the network on chip has become an urgent problem to be solved. Soft errors are mainly caused by interference, such as SEU (Single Event Upset), alpha ray, electron migration, noise, etc., which cause temporary err...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/70H04L1/00H04L45/28
Inventor 王嘉芳李本娟
Owner HEILONGJIANG UNIV
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