Method for improving write redundancy of high SRAM (static random access memory)

A write redundant, static random technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc.

Active Publication Date: 2012-10-17
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a method for improving the write redundancy of SRAM, so as to solve the prob

Method used

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  • Method for improving write redundancy of high SRAM (static random access memory)
  • Method for improving write redundancy of high SRAM (static random access memory)
  • Method for improving write redundancy of high SRAM (static random access memory)

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Embodiment approach

[0022] In the first embodiment of the present invention, please continue to refer to Figure 4a and Figure 4b shown. The above-mentioned lattice structure 18 is specifically a silicon carbide lattice structure. After the carbon implantation 17 process is performed, the source and drain ends of the NMOS device 12 and the source and drain ends of the pull-up tube 14 form a silicon carbide lattice structure.

[0023] In the second embodiment of the present invention, the above-mentioned covering layer 15 is photoresist.

[0024] In the third embodiment of the present invention, after carbon implantation 17 is performed on the NMOS device 12, the PMOS device 13 and the pull-up tube 14, an annealing process is required to finally make the source and drain ends of the NMOS device 12 and the pull-up tube 14 The source-drain two-terminal silicon carbide lattice structure.

[0025] To sum up, using the method of the present invention to improve the writing redundancy of the SRAM, ...

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Abstract

The invention discloses a method for improving write redundancy of a high SRAM (static random access memory). An NMOS (n-channel metal oxide semiconductor), a PMOS (p-channel metal oxide semiconductor) and an upper pulling pipe with cover layers are involved. The method comprises the following steps of: firstly simultaneously removing the cover layers of the NMOS device and the upper pulling pipe; and carrying out carbon injection on the PMOS and the upper pulling pipe with the cover layers so that a source drain end of the NMOS and a source drain end of the upper pull pipe form a crystal lattice structure and the tensile stress in a channel direction is improved. Through the method for improving the write redundancy of the high SRAM, disclosed by the invention, a carbon injection process is utilized to the source drain end of the upper pull pipe so that the tensile stress of the upper pull pipe in the channel direction is improved, the carrier mobility of the upper pull pipe is effectively reduced, the equivalent resistance of the upper pull pipe is increased, and simultaneously the write redundancy of an RAM (random-access memory) is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a method for improving the writing redundancy of a SRAM. Background technique [0002] Static random access memory (SRAM), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. figure 1 For a typical SRAM cell layout below 90nm, see figure 1 shown. It includes three levels of active region 4 , polysilicon gate 5 and contact hole 6 . The control tube 1 (Pass Gate) area is an NMOS device, the pull down tube (Pull Down MOS) 2 area is also an NMOS device, and the pull up tube (Pull Up MOS) 3 area is a PMOS device. [0003] Write margin (Write Margin) is an important parameter to measure the write performance of SRAM cells. figure 2 For the working schematic diagram of SRAM device when writing, please refer to figure 2 shown. Assuming that node 7 stores data...

Claims

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Application Information

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IPC IPC(8): H01L21/8244
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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