High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider

A technology of true single-phase clock and dual-mode frequency divider, which is applied in the field of frequency synthesizer to achieve the effect of increasing operating frequency, reducing power consumption, and reducing the number

Active Publication Date: 2012-10-17
JIANGSU CAS JUNSHINE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The traditional 2/3 dual-mode frequency divider cannot automatically turn off some unused D

Method used

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  • High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider
  • High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider
  • High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider

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[0019] The specific implementation of the present invention will be described in detail below in conjunction with the embodiments and the accompanying drawings, so that the technical solutions and beneficial effects of the present invention will be further explained.

[0020] The high-speed and low-power true single-phase clock 2D type 2 / 3 dual-mode frequency divider proposed by the present invention is used in a multi-mode frequency divider with a cascaded 2 / 3 frequency divider structure. The principle diagram of a 2 / 3 cascade structure multi-mode frequency divider is shown in 1. The multi-mode frequency divider is composed of cascaded 2 / 3 dual-mode frequency divider units cascaded, with m-level 2 / 3 dual-mode Take the cascade connection of frequency divider units as an example, the first stage is the highest frequency input, the corresponding output of the previous stage is used as the input of the next stage, and the output MODout of the next stage is fed back and combined with ...

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Abstract

The invention discloses a high-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider which comprises two D triggers, a mode switching control unit and a self-adaptive power consumption control unit, wherein the D triggers adopt synchronous triggering, and the CK end of each D trigger is connected with input clock, and the D end of each D trigger is connected with the output of a logic control unit; the input of the mode switching control unit is connected with frequency dividing ratio control end MODin and P; and the input of the self-adaptive power consumption control unit is connected with the output of the trigger unit and the output of the mode switching control unit. The control circuit provided by the invention is embedded and integrated in the D triggers, the D triggers adopt ratio logic to reduce the capacitive load so as to improve the working speed, the clock jitter introduced by the frequency divider is reduced by the synchronous working mode, under equal high-speed states, compared with the current of a current mode logic structure, the current of the true signal-phase clock is reduced from milliamp to microamp grade, the four D triggers in the prior art are reduced to two D triggers through optimization, the triggers are saved by a half, and correspondingly, the area and the power consumption are also reduced, and the self-adaptive power consumption control mode is configured according to the frequency dividing ratio, so that the power consumption of the dual-mode prescalar is further saved by 50%.

Description

technical field [0001] The invention relates to a frequency synthesizer with a PLL structure, in particular to a high-speed and low-power true single-phase clock 2D type 2 / 3 double-mode frequency divider. Background technique [0002] In a wireless communication system, the receiving system needs to restore the modulated radio frequency or microwave signal to the original signal or data, while in the transmitting system, the signal or data needs to be modulated to radio frequency or microwave frequency for long-distance transmission. In the process of receiving and sending, it is inseparable from the local oscillation signal, down-converting the receiving signal and up-converting the transmitting signal. [0003] The local oscillation signal is usually generated by a frequency synthesizer based on a phase-locked loop. The frequency synthesizer usually includes a voltage-controlled oscillator, a frequency and phase detector with a charge pump, a multi-mode frequency divider, ...

Claims

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Application Information

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IPC IPC(8): H03K23/44H03L7/18
Inventor 尹喜珍石坚甘业兵钱敏马成炎
Owner JIANGSU CAS JUNSHINE TECH
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