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Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure

An edge effect, copper electroplating technology, used in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of wafer contamination, unfavorable production costs, increase process complexity and production costs, and reduce edge effects. , the effect of reducing the total resistance and increasing the complexity of the process

Active Publication Date: 2015-04-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] But the resistivity of silver is not much different than the resistivity of copper, the reduction of the resistance value of the seed layer is limited, and the price of silver is much higher than the price of copper, which is not conducive to controlling production costs, and the prior art Requires additional process steps (putting the wafer into solution for reaction, spinning the wafer, etc.) and additional substances for the reduction reaction (AgNO 3 , reducing agent, etc.), it is easier to cause wafer contamination, and it increases the process complexity and production cost

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  • Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure
  • Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure
  • Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure

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Embodiment Construction

[0041] In the existing copper interconnect manufacturing process, as the thickness of the metal seed layer decreases, the resistance of the metal seed layer increases continuously, and the uniformity of the copper metal layer formed by electroplating becomes poor. In order to reduce the resistance of the metal seed layer and improve the uniformity of the copper metal layer formed by electroplating, the inventor formed two metal seed layers on the surface of the barrier layer and annealed the first metal seed layer, so that the second The resistance of a metal seed crystal layer is reduced, so the total resistance of the entire metal seed crystal layer is also reduced correspondingly, which improves the uniformity of the copper metal layer formed by electroplating.

[0042] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0043] The invention provides a method for reducing the edge effect in the cop...

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Abstract

The invention discloses a method for reducing a fringe effect in a copper plating process and a manufacturing method of a corresponding copper interconnection structure, wherein the method for reducing the fringe effect in the copper plating process comprises the steps of: forming a first metal seed crystal layer on the surface of a base; carrying out annealing treatment on the first metal seed crystal layer; forming a second metal seed crystal layer on the surface of the first metal seed crystal layer, and forming a copper metal layer on the surface of the second metal seed crystal layer. According to the method, two metal seed crystal layers are formed on the surface of a baffle layer; the first metal seed crystal layer is subjected to annealing treatment; the metal crystal particle of the annealed first metal seed crystal layer is agglutinated into a bump; the quality of crystal boundaries is reduced, and the resistance of the first metal seed crystal layer is reduced, so that the total resistance of the first metal seed crystal layer and the second metal seed crystal layer is also reduced, and the fringe effect in the copper plating process is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing edge effects in a copper electroplating process and a corresponding method for manufacturing a copper interconnection structure. Background technique [0002] In the prior art, the method for making a copper interconnect structure using a double damascene process includes the following steps: forming a barrier layer on the surface of the substrate; forming a copper seed layer on the surface of the barrier layer; forming a copper metal layer; planarizing the copper metal layer using chemical mechanical polishing (CMP). [0003] Please refer to the schematic structural diagram of the copper electroplating device in the prior art figure 1 , including: an electroplating container 11 full of copper sulfate solution 18; one side of the electroplating container 11 is provided with a copper sheet 16 as an anode, and the opposite side of the copper sheet 1...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 鲍宇平延磊
Owner SEMICON MFG INT (SHANGHAI) CORP