Circuit layout structure for detecting dishing on copper interconnect lines

Abstract

The invention discloses a circuit layout structure for detecting whether a saucer pit is produced by a copper interconnection line. The layout structure comprises a copper line of a bent structure and a copper line provided with comb teeth, wherein the comb teeth are arranged in a bent space; the two ends of the copper line of the bent structure are provided with two input end heads or output end heads respectively; and the two ends of the copper line provided with the comb teeth are provided with the input or output end heads respectively. Measurement can be performed by using the structure provided by the invention without being affected by the size of the line, an entire chip can be conveniently measured, and the uniformity of the chip CMP (Chemical Mechanical Polishing) is verified excellently.

Description

technical field [0001] The invention relates to the field of electrical measurement structure for detecting and evaluating the global planarization process of multilayer metal wiring, more specifically, relates to a circuit layout structure for detecting whether dish-shaped pits are generated in copper interconnection lines during chemical mechanical polishing. Background technique [0002] The current ultra-large-scale integrated circuit (ULSI) manufacturing has entered the ultra-deep sub-micron process stage. With the reduction of device size and the increase of operating frequency, interconnection delay and crosstalk have become the bottleneck restricting the performance of the entire circuit. From 0.13μm to 45nm and below technology nodes, integrated circuit interconnection adopts copper (Cu) interconnection and low dielectric constant (Low-K) dielectric technology to reduce the impact of various parasitic effects on circuit performance; at the same time, in order to o...

AI Technical Summary

Problems solved by technology

The effect of surface topography measurement is intuitive and reliable, but due to the limitations of the testing equipment used, there are still many limitations and deficiencies

The surface profiler based on the optical principle has a fast scanning speed and can obtain the three-dimensional topography of a large area of ​​the wafer surface in a short time, but its horizontal and vertical resolution is low, and it is gradually unsuitable for the process node below 90nm Copper interconnection CMP detection; the surface profiler based on the mechanical contact principle currently has a high vertical resolution, but the horizontal resolution is average, the scanning speed is slow, and it is easy to cause damage to the wafer surface; the atomic force microscope has little damage to the sample surface, and the resolution The detection rate is high, but the detection range is extremely limited. Usually, the reliable scanning area is only within tens of microns. At present, 300mm and 480mm have become the mainstream standard of silicon wafer size. The AFM detection is not only cumbersome to operate, but also complicated and inefficient.

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