SRAM circuit based on pnpn structure and its reading and writing method

Abstract

The invention provides a SRAM circuit based on a PNPN structure. The circuit comprises a plurality of bit lines, a plurality of word lines, a plurality of memory units respectively connected with every bit line and word line, a plurality of potential controlling devices connected in series at input terminals of the bit lines, and a plurality of inverters connected in series at output terminals of the bit lines. The circuit is characterized in that the memory units are double-terminal devices with PNPN diode structures. According to the SRAM circuit based on the PNPN structure, the PNPN diodes are adopted as the memory units, such that space occupation is low, power consumption is low, and SRAM large-scale integration and circuit integral performance improvement can be promoted. With the unique reversal characteristic of the PNPN diodes, logical values stored in the memory units can be conveniently rewritten by controlling the voltage differences of two terminals. Therefore, advantages of fast SRAM write operation and low error rate are provided. Also, because a resistor or MOSFET is connected at each bit line input terminal, and the inverters are connected at the output terminals, the reading speed of the SRAM circuit is high.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit device and a read-write method thereof, in particular to a SRAM circuit based on a PNPN structure and a read-write method thereof. Background technique [0002] Currently widely used memories are generally based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and are therefore referred to as MOS memories for short. The main product of MOS memory is random access memory (RAM), which is generally divided into random access memory (DRAM) and static random access memory (SRAM). SRAM relies on bistable circuits to store information, does not need to be refreshed, and has a fast working speed, which is suitable for high-speed cache memory. [0003] Existing SRAMs are generally composed of multiple transistors cross-coupled, for example, 6-tube, 8-tube or 9-tube units are used as their storage units, which have low integration and high power consumption. Although the new thin-film ...

AI Technical Summary

Problems solved by technology

However, because it is a two-terminal device, it is different from the electrical characteristics of the existing transistor three-terminal device, and its peripheral read and write control logic will also undergo major changes. The existing SRAM read and write circuits are no longer suitable for new storage units.

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