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Fabrication method of metal interconnection structure

A technology of a metal interconnection structure and a manufacturing method, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve the problems of difficulty in manufacturing the metal interconnection structure, and achieve the effects of reduced size, simple and easy-to-control precision

Active Publication Date: 2016-09-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If relying on the existing technology, it is very difficult to realize the metal interconnection structure of semiconductor devices with a feature size below 22nm

Method used

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  • Fabrication method of metal interconnection structure
  • Fabrication method of metal interconnection structure
  • Fabrication method of metal interconnection structure

Examples

Experimental program
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Effect test

Embodiment 1

[0047] In this embodiment, two-dimensional intersecting lines are used as a mask to etch and form the metal interconnection structure to be formed in the present invention, including through holes and trenches.

[0048] provide as figure 1 The semiconductor structure shown includes a semiconductor substrate 100 and a dielectric layer 110 formed on the semiconductor substrate 100 . Wherein, the subsequent step is to form the metal interconnection structure of the present invention in the dielectric layer 110 . As an embodiment, there is a first buffer layer 202 on the dielectric layer 110, and a first patterned hard mask layer 321 is formed on the first buffer layer 202. The first pattern of the first patterned hard mask layer 321 is Due to the limitation of the schematic diagram of multiple parallel line-shaped graphics with a distance of k, only the cross-section of the first pattern facing the paper is shown. The second buffer layer 204 is covered between and on the line ...

Embodiment 2

[0067] In this embodiment, the process of the present invention is described in detail by taking the formation of the metal interconnection structure of the present invention as an example.

[0068] Its implementation mainly includes the following steps:

[0069] Step S11: providing a semiconductor substrate 100, such as Figure 8 .

[0070] Wherein, the semiconductor substrate 100 can be a bulk silicon substrate, or a silicon germanium substrate, a group III-V element compound substrate (such as gallium arsenide, indium phosphide, gallium nitride, etc.), a silicon carbide substrate or A stacked structure, or a silicon-on-insulator structure, or a diamond substrate, or other semiconductor substrates known to those skilled in the art. The semiconductor substrate 100 may include devices such as MOS transistors, and may also include metal wires for electrical connection, which is not limited in the present invention. In this embodiment, the semiconductor substrate 100 is a bul...

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Abstract

The invention relates to a method for manufacturing a metal interconnection structure, which comprises the steps that a semiconductor substrate is provided, a dielectric layer, a first buffer layer, a first pattern hard mask layer, a second buffer layer and a second pattern hard mask layer are sequentially formed on the semiconductor substrate, the first pattern hard mask layer and the second pattern hard mask layer are line-shaped patterns which are mutually crossed, the second pattern hard mask layer and the first pattern hard mask layer are used as masks to etch the second buffer layer and the first buffer layer until the second buffer layer and the first buffer layer are exposed out of the dielectric layer so as to form a buffer layer pattern, the buffer layer pattern is used as a mask to etch the dielectric layer, the etching is stopped after the second buffer layer under the second pattern hard mask layer disappears and before the first buffer layer under the first pattern hard mask layer disappears so as to form a plurality of through holes and grooves connected to the at least two through holes in the dielectric layer, and the residual first buffer layer is removed. According to the manufacturing method disclosed by the invention, the buffer layer pattern is used as the mask to etch the dielectric layer, and the grooves and the through holes in the metal interconnection structure are formed simultaneously in the dielectric layer.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a metal interconnection structure. Background technique [0002] Metal interconnection in the manufacturing process of semiconductor integrated circuits refers to the connection made of conductive materials, such as aluminum, polysilicon or copper, to realize the interconnection between various devices on the chip, so as to transmit electrical signals to different parts of the chip. Generally, the metal interconnection structure includes a contact structure / via structure, and a metal interconnection groove. Among them, the contact structure refers to the structure that realizes the connection between the device in the chip and the first metal layer on the surface of the silicon wafer, and the through hole structure refers to the structure that realizes the formation of electrical connections from a certain metal layer to another adjacent metal la...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 夏建慧顾以理奚裴
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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