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Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof

A technology of source-drain contact and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as difficult to adopt and reduce source-drain contact resistance, achieve lower height, lower source-drain contact resistance, and improve performance effect

Active Publication Date: 2013-03-20
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0020] It can be seen that in the existing manufacturing technology of doped source-drain MOSFETs, it is difficult to use known methods to effectively reduce the source-drain contact resistance

Method used

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  • Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof
  • Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof
  • Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof

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Embodiment Construction

[0038]The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with exemplary embodiments, and a semiconductor device capable of effectively reducing source-drain contact resistance and a manufacturing method thereof are disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

[0039] Figure 2 to Figure 6 It is a schematic cross-sectional view of various steps of a semiconductor device capable of effectively reducing source-drain contact resistance and a manufacturing method thereo...

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Abstract

The invention discloses a metal-oxide -semiconductor field effect transistor (MOSFET) capable of effectively reducing source drain contact resistance and a manufacturing method of the MOSFET. The MOSFET capable of effectively reducing the source drain contact resistance and the manufacturing method of the MOSFET comprises substrates, a grid stacking structure at the bottom of the substrate, source-drain zones, grate side walls and metal silicide, wherein the source-drain zones are arranged in the substrates of the two sides of the grid stacking structure, the grating side walls are arranged on the substrates of the two sides of the grid stacking structure, and the metal silicide is placed in the source-drain zones of the two sides of the grating side walls. The MOSFET capable of effectively reducing the source drain contact resistance and the manufacturing method of the MOSFET is characterized in that a fractional condensation zone of doping cation is arranged on an interface of the metal silicide the source-drain zones. According to the MOSFET capable of effectively reducing the source drain contact resistance and the manufacturing method of the MOSFET, due to the fact that the fractional condensation zone of doping cation is arranged on the interface of source-drain contact of the metal silicide and the source-drain zones, schottky potential barrier height can be effectively reduced, the source-drain contact resistance is greatly reduced, and property of components is further improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a MOSFETS with effectively reduced source-drain contact resistance and a manufacturing method thereof. Background technique [0002] The continuous increase of IC integration requires the continuous reduction of device size, but the electrical operating voltage sometimes remains unchanged, which makes the electric field strength in the actual MOS device continue to increase. The high electric field brings a series of reliability problems, which degrades the performance of the device. For example, parasitic series resistance between the source and drain regions of a MOSFET will cause the equivalent operating voltage to drop. [0003] figure 1 Shown is a MOSFET with metal silicide on the heavily doped source and drain in the prior art, wherein a gate stack structure 200 composed of a gate dielectric layer 210 and a gate electrode 220 is formed on a subs...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/08H01L21/336
Inventor 罗军赵超
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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