A high-speed local bus access control interface module

Abstract

The invention provides an access control interface module of a high-speed local bus, wherein the interface module is solidified inside a field programmable gata array (FPGA) and is responsible for transmitting high-speed data. When the data is prepared to be transmitted, a local bus arbitration module is invoked to ensure the state of the bus, the write enable can be achieved by controlling the bus, and then address of sending the data to an external chip is ensured through an address bus, first data are sent to the external chip through a data bus. When third data is prepared to be received, the local bus arbitration module is invoked to ensure the state of the bus, a read enable can be achieved through a control bus, a data-invoking receiving module achieves the reception of the third data through the data bus. The interface module has the advantages of simplifying systematic design, saving space of hardware board cards, lessening volume of products and reducing power consumption. The interface module can be solidified inside a FPGA chip so as to improve safety, be communicated with other modules in the FPGA chip, simplify complexity of design of relative modules, improve operating speed and be convenient to use.

Description

technical field [0001] The invention relates to the communication field, in particular to a high-speed local bus access control interface module. Background technique [0002] When many high-speed chips currently use MCU access control, due to the non-specificity of the MCU operating system, the utilization rate of resources cannot achieve the best effect. Secondly, when hard encryption is required, the software data of the MCU needs to flow through the encryption hardware again to complete the requirement. The realization of these two steps can be completed independently by the FPGA chip. This module is such a product. It adopts FPGA hardware design and uses IP (IntellectualProperty) solid-core technology to complete the access to off-chip chips. At the same time, it can conveniently and naturally build this module on top of the hard encryption module. [0003] In the process of realizing the present invention, the inventor finds that at least the following disadvantages ...

AI Technical Summary

Problems solved by technology

[0004] In the design of high-speed interfaces that require a hard encryption background, especially in the design of Gigabit Ethernet, the existing interface design not only takes up more hardware board space, increases the power consumption of the system, and increases the production cost, but also The data transmission rate is reduced, and the intermediate process of data transmission is also increased, which increases errors

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