Wafer Level Test Structure and Test Methodology

Abstract

The invention discloses a wafer level test structure. Each test structure unit is composed of a first test structure, a first auxiliary test structure and a second auxiliary test structure. The composition structures of each test structure unit are respectively made of a plurality of parallelly arranged metal oxide semiconductor (MOS) tubes, grid electrodes of all the MOS tubes are arranged in floating mode, source areas and drain areas of the MOS tubes are connected in parallel and connected onto a pad, and a pad is further connected onto a substrate in leading out mode. The invention further discloses a wafer level test method which includes that leak currents of all composition structures of the test structure units are tested before and after high temperature and high pressure condition deterioration, the variable quantity of the leak currents is counted, and peripheral distributions with large leak current variable quantity are removed. By adopting the wafer level test structure and method, dislocated defects with shallow junction depth and introduced from an aureole ion injection area are screened out in wafer level testing, and therefore later stage packaging and testing cost can be reduced, and the testing period is shortened.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a wafer-level testing structure. The invention also relates to a wafer-level testing method. Background technique [0002] Defects introduced during wafer fabrication often lead to chip pin test (CP) failures or reliability (EFR) failures. Among them, the chip needle test is a test done before wafer dicing and packaging, which is a wafer-level test; while the EFR reliability test is generally performed after wafer dicing and packaging, which is a product-level test. As the device feature size (Critical Dimension) decreases and the process complexity increases, the impact of these micro-defects becomes more significant. For example, the advanced process uses halo ion implantation (Halo implant) to suppress the source-drain punchthrough (Punchthrough) caused by the short channel effect; May destroy the original unit cell structure and generate disloc...

AI Technical Summary

Problems solved by technology

Existing technology cannot screen out the above-mentioned shallow dislocation defects in wafer-level testing

Images